PART I: SOLUTIONS CHAPTER (Components of a computer: ALU and Control Unit (CPU), Memory, Input, ané Output. Functions of various components: CPU: It processes and stores binary data, wansfers data from and to memory and VO devices, and provides timing to all the operations. It includes ALU, register arrays, and control unit. ‘The ALU performs the arithmetic and logic operations, and the control unit provides timing. ‘Input - provides binary data as an input to the CPU. Output - accepts binary data from the CPU. A microprocessor functions as the CPU of a microcomputer, and includes the ALU, register arrays, and the control unit on one chip; it je manufactured using the LSL technology. On the Sther hand, the CPU is designed with various discret boards, Functionally, both are simian: however, technology and processes used for designing is different A microprocessor is one component of a microcomputer, and the microcomputer is complete computer consists of a microprocessor, memory, input, and output ‘See Summary: Scale oF Totagration Four bytes. “The machine language of the 8085 are the comamands to the microprocessor given in binary. ‘These are the binary instructions the processor can uncerstand and execute. ‘The assembly Ianguage comprise ef mnemonics (group of letters (o represent commands) assigned by the manufacturer For the convenionee of the users, 9, 10, 11. See Summary: Computer Languages 12. ‘The assembly language mnemonics represent instructions to the microprocessor; therefore, ‘hen they are wanslated into machine language. there is one-to-one correspondenc= between the mnemonics and the machine code. The assembly language programs are compact, require less memory space, and are efficient. ‘The high level languages arc written, in English- like statements, and when these statements are translated in machine language. the ‘object code tends to be large, and requires large memory. ‘The execution of the programs ‘written in high level languages is less efficient than that of assembly language programs15, 14, See Summary: Computer Languages 15. 16. ASCII codes in Hex: A= 41, 5A, snd m=6D s Summary: Computer Languages CHAPTER? is 2 10 12 ‘Memory Read, Memory Write, VO Read, and YO Write A bus is group of lines (wires or conductors) which carry digital information. “The fiction of the address bus sto camry binary adress of a memory Jocation or an YO device. The address bur ig unidirectional, and the inforaation flows from the MPU to peripherals and memory “A microprocessor with 14addeeas lines is capable of addressing 16K (2) memory ovations 21 adress Lines, ‘Data bytes are transfered in both directions between the MPU and memory/peripherals, TOR (VO Read), IOW (VO Write), MEMR (Memory Read, sad MEMW (Memory Write) 1m memory write operation, the control siznal required is MEMW, and the direotion of the data flow is fom the MPU to memory. “The accumulators an §-bit register anditiea partof the ALU. All8-bit arithmetic and logic ‘operations are performed in relation to the accumulator conient, and thereeult is storedinthe steurnulator (with a few exceptions) A fing is the output of a given Mip-flop to indieate certain data conditions. ‘The program counter and the stack pointer store memory sddzesees of 16 bits. ‘The program counter always points to the next memory location; thersfore, the content of the program counter will be 2058H, 128 registers and 128 X 4 = 512 memory cells 1024 bits are can be stored by this chip; however, it can not be specified as a 128-byte _memary chip because the byte indicates S-bit memory repisters; this chip has 4bit registers.1s, 16. 16 18. 21 2, Fs 24, 2s. 26. 28 29, 30, 3. 32. 33, 34. S-bit word size 8 chips. A chips. 32 chips. ‘The WR signal enables the input bulfer of s memory chip 90 that information ean be stored (oritton) in the Selected memory register 1 adress Hines, 16 pages and the last location is 2FFFH. ‘The stating address is FBOOH, end the memory map is PROOKT to FRFPEL “The staring address ie: EOOOH, ‘The address ranges ftom FFOOH to FEFFEL “The address ofthe selected register: 1000 0000 0100 0111 = 047H ‘The memory map ranges fkom 200011 to 23FFH. ‘The address of the selected register: 0010 0000 1111 1000 = 20% 8 adress lines are required for a peripheral VO port, and 16 address lines are required for 8 memory-mapped VO port ‘Tri-state dovicos are logle devieet with three states; the ted tate ie high impedance. Ina ‘bus-orlented system, devices are connected in parallel, and the buses are capable of driving fone TTL logic device. The MPU communicates with one peripheral st a time, and odor ‘penpherals are placed in igh impedance to svoid bus loading, “High impedance tae From to. ‘None. The decoder is not enabled: all outpet lines will be high, “The line 6 (0 (001 (Complement of 10)35 36. 3. 38. ‘A transparent latch ga flip-flop; its ourput changes according to input when the clock signal ig high, and it latches the input when the clock goes low. The latch [s necessary for output dovicos to rotain the result otherwise, the resue will disappear. “The high-order address lines: A12-A1S, the low-order address lines: AO-A10, and the don't care line: ALL ‘This answer assumes the memory chips are 2048 X 4 AIS AIA AI3 AIZ ALL ALO AS ASAT AG AS A4.A3 AZ. AL AG 1 1 1 10 000000000 0 o=F000H 1 1 bop bo bp aad dab td PRR ‘The memory occupies the memory space from FOOOH to FFFFH. The don't care line Al ‘generates additional address range. This is a 2K memory chip that oceupies 4K of memory Space in the map, thus wasting 2K of memory space. IF A11 is assured to be at logic O as in @. 27, the address range is: FOOOH to F7FEH and if tis assumed to be at logic 1, the fddress range (also called foldback memory space) is: F800H to FFFFHL, CHAPTER 3 “The ALE signal goes high at the boginning of each machine cycle indicating the availabiliey ‘of an address on the address bus, and the signal is used to latch the low-order address bus. ‘The IO/M signal ie a satus signal indicating whether the machine cycle is VO or memory ‘operation. ‘The TO/M signal is combined with the RD and WR control signals to generate TOR, 1OW, MEMR and MEMW control signals. “The low-order bus AD7-ADO is used for two purposes. In the carlicr part of a machine cele, the bus is used forthe low order address of a memory location the 8085 is accessing. land in the latter part of the cycle the bus is used for data. By demultiplexing the bus, he ‘Midrese and the data are kept separate. {In Fig. 3.22, the input signal RD ané WR cannot be low atthe same time. Therefore, the ‘Valid combinations ofthe input signals are:n 2. 13. 14. OM RD WR Output Signal 2 © 0 invaiia 2 0 3 MEM 2 1 0 Oo, Mew 0 1 1G Erelevant 16 0G nvata 10 1) 6 10R 1 1 6 & Tow P11 Os elevant See the answer of Q3. RD and WR cannot be active simultaneously Mand RD active Mand WR active Both RD and WR are inactive [RD and WR cannot be active simukaneousty TO and RD active 10 and WR active Both RD and WR are inactive In Fig. 3.25, the 7418139 is enabled when IO/M is low. Therefore, the following memory ‘contol signals can be generated. ‘The output of the latch will be OSH; however, it will be not be latched until the ALE goes low. ‘The output of the latch is OSH. At 72, the ALE is low; therefore, the latch will not be ‘enabled, and it will continue to hold the previously latched byte (OSI. ‘The crystal stoquency should be ~ 2.2 MEz because the oscillator logie divides the input Frequency by wo. See the steps on page 66/67, Example 3.1 ‘The sum of 87H 79H = 100K. Therefore, the accumulator will have OOH, snd the flows willbe 0, C¥ = 1.2=1 20601. The program counter always points tothe next mechine code to be fetched. IST X 2 micro-tce = 3.6 micro-see, (AIS-A8) = 2081, (AD7-ADO) [RD and JO/M are asserted low. as 47H, (PC) = 207619, 20. a 22, 23, 25, 28. ‘The second machine eycle is Memory Read; the processor reads the contents of memory in register B, apd the contol signal is RD, “The fourth machine cycle is Memory Read; the processor reads the contents of memory in the accuanlator. (A1S-A0) = 20501 (AD7-ADO) as data bus = Contents of location 205014 (Refer to Instruction Sot on pages 696-699) UBB = OF (Opeode Fetch) ‘ADI 47H = OF, MR (Memory Read) STA 205011 = OF, MR, MR, MW (Memory Write) PUSHB = OF, MW, MW. ‘Memory map: 6000H to 6FFFH ‘Memory map: 8000H to SFFFH_ OR gate Connect RD to OF of the memory chip and IOMM to R2 of the decoder AISAISAISAIZ AI] AIO A9 ABA7 AGAS AS AS A2 AL AO 0 0 1 6 1 © 60000 00000 =2800% 1 I boat a aa ata eer ‘Total range 16K. Map = S000H to BFFFEL A data byte entered at location 2100H will be accepted and stored at location 2000H. The ‘adarees lines A 10, AO, and AS aronotbeing used for memory addressing: therefore, they ean ‘assume O oF 1 (dont care) logie state wich sevults into multiple addresses forthe same ‘memory locations ‘Memory address: 0800H-OSFFH, and the foldback memory ranges from 0900 to OF FFE. ‘Memory map: 3800H - 3FFFEL {In Figure 3.19, three lines are dant care which can have (2) eight combinations. This the ‘memory chip Will occupy the memory space equal to citht tes is ize ROMI: 0000H - LFFFE, ROM2: E0001 - FFFFH, R/WMI: 8000 - $3FFH