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Experiment No. 2: Aim: A) D Flip-Flop: Synchronous VHDL Code

The document describes VHDL code and simulations for several sequential logic circuits including: 1) Synchronous and asynchronous D flip-flops 2) Synchronous and asynchronous loadable registers 3) A latch The VHDL code implements each circuit and is then simulated and converted to an RTL schematic.

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Rahul Mishra
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© Attribution Non-Commercial (BY-NC)
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105 views

Experiment No. 2: Aim: A) D Flip-Flop: Synchronous VHDL Code

The document describes VHDL code and simulations for several sequential logic circuits including: 1) Synchronous and asynchronous D flip-flops 2) Synchronous and asynchronous loadable registers 3) A latch The VHDL code implements each circuit and is then simulated and converted to an RTL schematic.

Uploaded by

Rahul Mishra
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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EXPERIMENT NO.

2
AIM : Model a flip-flop, register and a latch in VHDL. Implement with asynchronous and synchronous
reset.

a) D flip-flop : Synchronous
VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is
port (d,clk,rst : IN std_logic;
q : OUT std_logic);
end dff;

architecture Behavioral of dff is


begin
process(clk)
begin
if (clk='1' and clk'event) then
if (rst='1') then
q <= '0';
elsif (rst='0') then
q <=d;
end if;
end if;
end process;
end Behavioral;

SIMULATION :

RTL SCHEMATIC :
b) D flip-flop : ASYNCHRONOUS

VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFFASR is
port
(ASR,D,CLK: IN STD_LOGIC;
Q :OUT STD_LOGIC);
end DFFASR;
architecture Behavioral of DFFASR is
begin
process(CLK,ASR)
begin
if(ASR='1') then
Q <= '0';
elsif(CLK'EVENT and CLK ='1') then
Q <= D;
end if;
end process;
end Behavioral;

SIMULATION :
RTL SCHEMATIC :

c) LOADABLE REGISTER : Synchronous

VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LRSR is
port
( Din: in std_logic_vector(7 downto 0);
Qout: out std_logic_vector(7 downto 0);
Load,clk,reset: in std_logic );
end LRSR;

architecture Behavioral of LRSR is


signal NS, PS : std_logic_vector(7 downto 0) := "01010101";
begin
abc:process(clk)
begin
if(clk'event and clk='1')then
if(Reset='1') then
PS<= "00000000";
else
PS<=NS;
end if;
end if;
end process abc;

def:process(Din, Load, PS)


begin
NS<=PS;
if(Load='1') then
NS<=Din;
end if;
end process def;
Qout<=PS;
end Behavioral;

SIMULATION :

RTL SCHEMATIC :

d) LOADABLE REGISTER : Asynchronous

VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LRASR is
port
( Din: in std_logic_vector(7 downto 0);
Qout: out std_logic_vector(7 downto 0);
Load,clk,reset: in std_logic );
end LRASR;
architecture Behavioral of LRASR is
signal NS, PS : std_logic_vector(7 downto 0) := "01010101";
begin
abc:process(clk,Reset)
begin
if(Reset='1') then
PS<= "00000000";
elsif(clk'event and clk='1')then
PS<=NS;
end if;
end process abc;

def:process(Din, Load, PS)


begin
NS<=PS;
if(Load='1') then
NS<=Din;
end if;
end process def;
Qout<=PS;
end Behavioral;

SIMULATION :

RTL SCHEMATIC :
e) LATCH

VHDL CODE :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity latch is
port (d,rst : IN std_logic;
q : OUT std_logic);
end latch;

architecture Behavioral of latch is


begin
process(d,rst)
begin
if (rst='1') then
q <= '0';
elsif (rst='0') then
q <=d;
end if;
end process;
end Behavioral;

SIMULATION :

RTL SCHEMATIC :

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