Interfacing I/O devices

and peripherals
Addressing schemes:

i) Memory-mapped I/O
ii) I/O mapped I/O.
Memory mapped I/O
• An I/O device is treated as a memory location;
hence a 16-bit address is assigned to it.
• In memory mapped I/O all data transfer instructions of µP
are applicable to memory as well as I/O devices.
• Thus, if instruction MOV M, A is used, it will transfer the
data from accumulator to an address given by the register
pair HL. If the memory pointer points to the address that
pertains to memory device the content of accumulator will
be transfer to that memory location. However, if this
pertains to I/O device the content of accumulator will be
transfer to that I/O device alone. Memory mapped I/O can
be used in all µP system.
• I/O devices are accessed by memory READ-WRITE cycles
I/O mapped I/O
• I/O devices are treated as distinct form memory devices.
• To identify the I/O device µP has to send a proper
control signal on I/O line along with the 8-bit port
address.
• In this scheme the CPU uses instructions like IN 8-bit
port addr or OUT 8-bit port addr for I/O Read/Write
operations.
• The main disadvantage of this scheme is the timing
incompatibility of the I/O devices with the µP, some
times it leads to interfacing problems
• I/O mapping is done by I/O READ-WRITE cycles.
 Comparison between Memory Mapping and I/O Mapping

Memory Mapping I/O mapping

1. The device is accessed by memory 1. The device is accessed by I/O read
read or write cycle or write cycle
2. 16-bit addresses are provided for 2. 8-bit addresses are provided for
I/O devices I/O devices
3. The I/O port or peripheral can be 3. In I/O mapping IN and OUT
treated as memory location so all instructions are used for data
the instructions related to memory transfer between I/O device and
can be used for data transfer the µP.
between I/O device and the µP. 4. The data transfer can take place
4. The data can be transferred from only between accumulator and the
any register to port and vice-versa. ports.
5. In memory mapping a large 5. In I/O mapping only 256 I/O ports
number of I/O ports can be can be interfaced
interfaced. 6. I/O mapping is suitable for large
6. Memory mapping is used for systems, where the memory
small systems, where the memory requirement is large.
requirement is less.
Memory interfacing:
• In a microprocessor based system the memory devices (EPROM/
RAM) {and I/O devices} are also important as the CPU itself,
because memory is the device where the system program and data
resides. While executing a program, the microprocessor needs to
access memory quite frequently to read instruction codes and to
read / write data. So we need to interface memory devices to the
microprocessor.

• 8085 Microprocessor has total 16 address lines, therefore it can

access (address) 64K bytes of memory. The term “Memory
Interfacing” means, to “PLACE” available memory chip (2K, 4K, 8K
or 16K – EPROM or RAM) within 64K bytes address range. This is
also referred to as “Mapping”.
• Mapping decides “Address” of the memory component.
For interfacing memory devices to 8085 microprocessor, following
steps are to be kept in mind:

1. 8085 microprocessor can access 64K bytes of memory, since its address bus is 16-bit. But it is
not always necessary to use full 64K bytes of address range. The total memory size depends
upon the application.
2. Generally EPROM(s) is used as a program memory and RAM(s) as a data memory and total
address space is shared by both.
3. The size of the program memory and data memory depends on the type of application.
4. It is not necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and RAMs as
per requirement.
5. We can place EPROM/ RAM anywhere in full 64K bytes of address space. But at least one
program memory (EPROM) should be located from address 0000H, since RESET address of 8085
microprocessor is 0000H.
6. It is not necessary to locate EPROM and RAM in consecutive memory address.
7. Wherever we place memory, but we have to decide address for the same. Address must be 16-
bit.
8. A memory chip of given size can be address with different addresses.
9. Once the address is finalized, we have to use a digital circuit, which is normally referred to as
“Decoder Logic”, to decode address and locate a desired memory register. Decoder logic is
nothing but a combinational logic circuit. One can use Logic gates or 3:8 decoder (IC 74LS138) to
built or design Decoder Logic. Generally 3:8 decoders is preferred in 8085 microprocessor base
systems for decoder logic, since it reduces hardware and with one decoder circuit we can select 8
different chips.
 To understand decoder logic let us take an example:

Example: Interface a 4K X 8 RAM to 8085 microprocessor with

 starting address C000H.
4K memory requires 12 address lines, 2 12 = 4096

Step – 1 : Memory size is 4K. Thus total address lines required will be A 11 – A0
and remaining 4 lines A15 – A12 can be used for decoder logic (chip
select logic)
Step – 2 : Address range for 4K RAM starting from C000H will be
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C000H
Starting
Address
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 CFFFH
End Address
← Used by → ← Directly given to memory chip →
(Size = 4K)
decoder logic
Step – 3 : A15 – A12 lines are to be used for decoder logic ( chip select logic).
Since chip select of RAM is active low, A15 – A12 = (1100)2 – when
given to decoder,CS decoder A
output
– A - are
15 should
chip
12
toselect
be used godecoder
logic).
for LOWlogic
Since and( for any other
value of A15 – A12 decoder output should be HIGH.
Step – 4 : Below given figure shows one of the way to implement Step – 3.

A15

G2B G2A G1 7
6
A14 C 5
3:8 4
CS
A13 B Decoder 3
A12 72138 2
A
1
0
Step – 5 : Interfacing 4K X 8 RAM to 8085 μP with starting address C000H
will be as shown

8 Lines A7 - A0
A7 - A 0
8 Lines D7 - D0
D 7 - D0
4 Lines A11 - A8 4K X 8
A11 - A8 RAM
A15

Basic CS RD WR

8085
G2B G2A G1 7
p 6
A14 C 5
3:8 4
A13 B Decoder 3
A12 72138 2
A
1
0

MEMR
MEMW
Absolute decoding:

To address (interface) a memory of given size, required number of

address lines are directly connected to memory chip and remaining all
the high order address lines are used for designing decoder logic (chip
select logic). Due to this, memory Chip is selected only when a specific
(unique) bit pattern (address) appears on the address lines. Therefore
this type of decoding technique is referred to as “Absolute Decoding
or Full Decoding”.

Absolute decoding is preferred in microprocessor based system

where memory size is large.
Linear or Partial Decoding:

In small microprocessor based systems wherein the memory size is

small we don’t required all 16 address lines to address a desired
memory location. So if few address lines are not used it will work.
Unused address lines are labeled as don’t care (X) lines. Simply
ignoring few address lines in decoding technique is referred to as
“Partial or Linear Decoding”.

But due to this we come across very interesting phenomena normally

referred as “Shadows of memory or Folded memory ”.

In partial decoding the same memory can be addressed by multiple

addresses called Shadow addresses. Once the shadow address is
finalized and if we want to map one more memory chip, then we
have to take a precaution that there is no overlapping of addresses
including shadow addresses.

Advantage of partial decoding is – hardware for decoding logic can be

reduced or can be eliminated. It reduces the cost of decoding circuit.
Comparison between absolute decoding and partial decoding:

Absolute (Full) decoding Partial (Linear) decoding

1. All higher address lines are used in 1. Few high order address lines are
decoding logic to select the ignored in decoder logic to select
memory or I/O device memory or I/O device.
2. More hardware is required to 2. Hardware required to design
design decoder logic decoder logic is small or it can be
3. Higher cost for decoding circuit eliminated
4. No multiple addresses 3. Low cost for decoding circuit
5. Used in large systems. 4. Disadvantage of multiple
addressing (Shadow or folded
addresses)
5. Used in small systems.