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Low Power Vlsi in CMOS

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73 views

Low Power Vlsi in CMOS

Uploaded by

avmeee
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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LOW POWER VLSI

By,
K.Nagendra
06S11A0421
Why worry about power?
--Heat Dissipation
Microprocessor power Consumption
Why we go to Low Power..
PORTABILITY:
Enhanced run-time, Reduced weight, Reduced
volume, Low cost operation
High Performance:
Low-cost cooling, Low-cost packaging, Low-cost
operation
RELIABILITY:
Avoid thermal problems
Avoid scaling related problems
Speed/Power performance for
available Technologies
Where Does Power Go In CMOS
• Dynamic Power Consumption :
Charging and Discharging Capacitors
• Short Circuit Currents :
Short circuit path between supply rails during
switching
• Leakage:
Leakage diodes and transistors
Ptotal = PDYN + PSC + PLeakage
=CLVDDF+VDDIPEAK{(Tr + Tf)/2}F+VDD ILEAK
Dynamic Power Consumption

Energy/transition = CL * Vdd2
Dynamic Power Consumption
• Power = Energy / Transition * transition rate
2
= CL* V * f
dd

• So, power is proportional to Vdd , f ,CL

• Power dissipation is data dependent


Function of switching activity
Reducing Vdd
• Power P is proportional to square of V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 5, 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
• Further decreasing may cause affect to Threshold
voltage
• Relatively independent of logic function and style.
• Power Delay Product Improves with lowering Vdd.
• By reducing Vdd Noise margin will be affected
Noise Margin

• NML = VIL - VOL


• NMH = VOH - VIH
Power Consumption is Data
Dependent
Ex: Static 2 i/p NOR Gate

A A B Y P(A=1) = ½
P(B=1) = ½
0 0 1
B Then
0 1 0
Y P(out=1) = ¼
1 0 0 P(out=0) = 1-P(out=1)
=1-1/4 = ¾
1 1 0
P(0->1) =
P(out=1).P(out=0)
= ¾ * ¼ = 3/16
Transition Probability of 2-input
NOR Gate
A
B
Y
Transition Probabilities for Basic
Gates
P0 -> 1
AND (1-Pa * Pb) Pa Pb
OR (1-Pa)(1-Pb)(1-(1-Pa)(1-Pb))
EXOR (1-(Pa + Pb - 2Pa * Pb)) (Pa + Pb -
2Pa * Pb)
Switching Activity for Static CMOS
P0 -> 1 = P0 * P1
How about Dynamic Circuits..?

Clk Mp  Power is only


Out dissipated when
In1 CL out=0
In2 PDN
In3
 Ceff = P(out=0) * CL
Clk Me

Two phase operation


Precharge (CLK = 0)
Evaluate (CLK = 1)
2 input NOR gate
A B Y P(A=1) = ½
P(B=1) = ½
0 0 1
P(out=0) = ¾
0 1 0 Ceff = ¾ * CL
1 0 0
 Switching activity is
1 1 0 always Higher in
Dynamic Circuits
Transition Probabilities For
Dynamic GATES
P0 -> 1
AND (1-Pa * Pb)

OR (1-Pa)(1-Pb)

EXOR (1-(Pa + Pb - 2Pa * Pb))


Switching Activity for Precharged Dynamic
Gates
Glitching…
• Glitching refers to spurious and unwanted
transitions that occur before a node settle
down to its final steady-state value.
• Glitching often arises when paths with
unbalanced propagation delay converges
at the same point in the circuit.
• The dissipation caused by the spurious
transitions can reach up to 25% of the total
dissipation for some circuits.
Glitching in Static CMOS

 Each gate has


Unit delay
 Input A, B, C
arrive at same
time.
 No glitching in
dynamic circuits
How to Cope With Glitching..?
Short Circuit Currents
• Short circuit currents are encountered only
in static design.
• In static CMOS circuits the flow current
from VDD to GND during Switching when
both NMOS and PMOS conducting
Simultaneously.
• Such path never exists in a dynamic
circuits.
Short Circuit Currents
Vdd

Vout NMOS off


Vin Vout
PMOS res

2.5
NMOS sat
CL
PMOS res

2
NMOS sat

1.5
0.15
PMOS sat

1
0.10 NMOS res
IV DD (mA)

PMOS sat NMOS res


0.5

0.05 PMOS off

0 .5 1 1 .5 2 2 .5 Vin
0.0 1.0 2.0 3.0 4.0 5.0
Vin (V)
Impact of rise/fall time on Short-
Circuit Currents
V DD
V DD

V in V out
V in V out
CL
CL

Large Capacitive Load Small capacitive Load


 The input through the  Output fall time is
transient region before the Substantially smaller than
output start to change the input rise time
Short-Circuit energy as a function
of slope ratio
• Short-Circuit energy dissipation (normalized with
respect to zero i/p rise time energy) for a static
CMOS.
• The power dissipation due to short circuit
currents is minimized by matching the rise/fall
times of the input and output signals.
• Short-Circuit reduced by lower the Supply
Voltage.
Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-Threshold current Dominant factor


Sub-Threshold Current Dominant Factor
Static Power Consumption
Vdd
 Dominates over dynamic
consumption
Istat
Vout
 Not a function of Switching
Frequency.
CL
Vin =5V
 Reduce switching activity

 Reduce physical
Pstat = P(In=1) .Vdd . Istat capacitance

nates over dynamic consumption


System-Level optimization : Power
Management

• In event-driven application, large amounts of


power are wasted while the system is in idle-
mode.
• The power consumption can be reduced
significantly by using power management
scheme to shunt down idle component.
Conclusion
• Thus the low power can be achieved by
decreasing Vdd to certain level.
• As leakage current cannot be reduced, the short
circuit currents are eliminated by dynamic
circuits.
• The power dissipation due to short circuit
currents is minimized by matching the rise/fall
times of the input and output signals
• Glitching makes power to dissipate so it is
reduced by cope process
References
• Digital Integrated Circuits –JAN M.RABAEY
• Encyclopedia of computer science and
technology,1995.
• VLSI Design Techniques for Analog and Digital
Circuits –Randall L.Geiger, Phillip E.Allen.
• Basic VLSI Design A.PUCKNELL.
• Low-Power CMOS Design “IEEE journal of solid
state circuit -pages 472-484,Aprill 1992”.
THANK
‘U’

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