Intel 80486

Microprocessor

Submitted By –
Sukhdeep Singh (4017)
Supreet Kaur (4018)
M.Tech (CSE - I)
 Introduction
• The Intel i486, otherwise known as the 80486, was the first tightly
pipelined x86 design.
• Introduced in 1989, it was also the first x86 chip to use more than a
million transistors, due to a large on-chip cache and an integrated
floating point unit.
• It represents a fourth generation of binary compatible CPUs since the
original 8086 of 1978, and it was the second 32-bit x86 design after
the 80386.
• A 50 MHz 80486 was reportedly able to perform 41 million
instructions per second and was able to reach 50 MIPS peak.
 Features
• The 32-bit 80486 is the next evolutionary step up from the80386.
• High Integration
o On-chip 8K Code and Data cache
o Floating Point Unit
o Paged, Virtual Memory Management
• 168-pin PGA package
• Multiprocessor Support
o Multiprocessor Instructions
o Cache Consistency Protocols
• Built in math coprocessor.
o Same as in 80387 processor used with a 80386
o Being integrated on the chip allows it to execute math instructions
about three times as fast as a 80386/387 combination.
Signal Interface
 Memory Management
• The memory system for the 486 is identical to 386 microprocessor.
The 486 contains 4G bytes of memory beginning at location
00000000H and ending at FFFFFFFFH.
• The major change to the memory system is internal to 486 in the
form of 8K byte cache memory, which speeds the execution of
instructions and the acquisition of data.
• Another addition is the parity checker/ generator built into the 80486
microprocessor.
• Parity Checker / Generator : Parity is often used to determine if data
are correctly read from a memory location. INTEL has incorporated
an internal parity generator / decoder.
• Parity is generated by the 80486 during each write cycle.
• The cache is organised as a 4 way set associative cache with each
location containing 16 bytes or 4 doublewords of data.
• Control register CR0 is used to control the cache with two new
control bits not present in the 80386 microprocessor.
 Memory Management (contd.)
• This includes a paging unit to allow any 4K byte block of physical
memory to be assigned to any 4K byte block of linear memory.
• The only difference between 80386 and 80486 memory-management
system is paging.
• The 80486 paging system can disable caching for section of
translation memory pages, while the 80386 could not.
• If these are compared with 80386 entries, the addition of two new
control bits is observed ( PWT and PCD ). • The page write through
and page cache disable bits control caching.
Page Directory And Page Table Entries
 Models
• i486DX — The original chip (without any clock doubling).
• i486DX-S — SL Enhanced 486DX
• i486DXL — A 486DX with SMM (System Management Mode), stop
clock, and power saving features.
• i486SX — an i486DX with the FPU part disabled or missing. Early
variants were parts with disabled FPUs, later versions had the FPU
removed from the die to reduce area and hence cost.
• i486SX-S — SL Enhanced 486SX
• i486SXL — A 486SX with SMM (System Management Mode), stop
clock, and power saving features.
• i486DX2 — the internal processor clock runs at twice the clock rate
of the external bus clock.
• i486SX2 — i486DX2 with the FPU disabled.
• i486SL — low power version of the i486DX, reduced VCore, power
conservation circuitry - mainly for use in portable computers.
 Models (Contd.)
• i486SL-NM — i486SL based on i486SX
• i487SX — i486DX with a slightly different pinout sold as an FPU
upgrade to i486SX systems; it was widely documented that an
i487SX when installed completely disabled the existing i486SX on
the motherboard, replacing it.
• i486 OverDrive — i486SX, i486SX2, i486DX2 or i486DX4. Marked
as upgrade processors, some models had different pinouts or voltage
handling abilities from 'standard' chips of the same speed stepping.
Fitted to a coprocessor or "OverDrive" socket on the motherboard,
worked the same as the i487SX.
• i486DX4 — designed to run at triple clock rate (not quadruple as
often believed; the DX3, which was meant to run at 2.5x the clock
speed, was never released). DX4 models that featured write-back
cache were identified by an "&EW" laser etched into their top surface,
while the write-through models were identified by "&E".
 80386 vs 80486
• The successor to the 80386 processor, Intel 80486 (i486) included
many changes to its micro architecture that resulted in significant
performance improvements:
• 8 KB unified level 1 cache for code and data was added to the CPU.
In later versions of the 80486 the size of level 1 cache was increased
to 16 KB.
• Execution time of instructions was significantly reduced. Many load,
store and arithmetic instructions executed in just one cycle
(assuming that the data was already in the cache).
• Intel 486 featured much faster bus transfers - 1 CPU cycle as
opposed to two or more CPU cycles for the 80386 bus.
• Floating-point unit was integrated into 80486DX CPUs. This
eliminated delay in communications between the CPU and FPU.
Furthermore, all floating-point instructions were optimized - they
required fewer number of CPU cycles to execute.
• Clock-doubling and clock-tripling technology was introduced in faster
versions of Intel 80486 CPU.
 80386 vs 80486 (Contd.)
• Power management features and System Management Mode (SMM)
became a standard feature of the processor.
• An 8 KB on-chip SRAM cache stores the most commonly used
instructions and data (16 KB and/or write-back on some later
models). The 386 had no such internal cache but supported a slower
off-chip cache.
• Tightly coupled pipelining allows the 486 to complete a simple
instruction like ALU reg,reg or ALU reg,im every clock cycle. The 386
needed two clock cycles for this.
• Integrated FPU (disabled or absent in SX models) with a dedicated
local bus gives faster floating point calculations compared to the
i386+i387 combination.
• Improved MMU performance.
• The 486 has a 32-bit data bus and a 32-bit address bus. This
required either four matched 30-pin (8-bit) SIMMs or one 72-pin (32-
bit) SIMM on a typical PC motherboard. The 32-bit address bus
means that 4 GB of memory can be directly addressed.
 Obsolescence
• Windows 95 signaled the end of the 486 era due to its high memory
requirements (16 MB to perform as well as Windows 3.x with just 8
MB).
• Many 486 users at that time were running eight 1 MB 30-pin SIMMs
on a motherboard with as many SIMM sockets, leaving no available
room for expansion.
• The 486s were used as budget machines for people who could not
afford the latest computers, until around 2001, when Windows 95
support ended and Windows 98, ME, 2000, and XP required much
more powerful computers to perform well.
• A small proportion of 486s stayed in service much longer in
dedicated roles of the desktop as servers, network hosts, routers,
terminal emulators, process control systems, etc., running various
operating systems other than Microsoft Windows 98 and later.
• Some people also kept 486-based PCs for playing classic games
under MS-DOS.
Thank You