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Verilog HDL A Guide To Digital Design and Synthesis Samir Palnitkar Sunsoft Press 1996

This document is a guide to digital design and synthesis using Verilog HDL written by Samir Palnitkar and published by SunSoft Press in 1996. It is divided into three parts, with part one covering basic Verilog topics like modeling concepts, modules, ports, gate-level modeling, dataflow modeling, and behavioral modeling. Part two covers more advanced topics such as timing, switch-level modeling, user-defined primitives, and logic synthesis. Part three contains appendices with additional reference information on topics like strength modeling, PLI routines, keywords, and examples.

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Pramod Reddy R
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125 views

Verilog HDL A Guide To Digital Design and Synthesis Samir Palnitkar Sunsoft Press 1996

This document is a guide to digital design and synthesis using Verilog HDL written by Samir Palnitkar and published by SunSoft Press in 1996. It is divided into three parts, with part one covering basic Verilog topics like modeling concepts, modules, ports, gate-level modeling, dataflow modeling, and behavioral modeling. Part two covers more advanced topics such as timing, switch-level modeling, user-defined primitives, and logic synthesis. Part three contains appendices with additional reference information on topics like strength modeling, PLI routines, keywords, and examples.

Uploaded by

Pramod Reddy R
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Verilog HDL

A guide to Digital Design


and Synthesis
Samir Palnitkar
SunSoft Press
1996
PART 1 BASIC VERILOG TOPICS 1
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
PART 2 Advance Verilog Topics 191
10 Timing and Delays 193
11 Switch-Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
PART3 APPENDICES 319
A Strength Modeling and Advanced Net Definitions 321
B List of PLI Rountines 327
C List of Keywords, System Tasks, and Compiler Directives 343
D Formal Syntax Definition 345
E Verilog Tidbits 363
F Verilog Examples 367

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