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Nand Layout

The document contains SPICE netlist code that models the behavior of a basic logic gate circuit with 4 transistors. It defines 4 voltage sources to provide inputs to nodes A and B and ground. It also defines the 4 MOSFET transistors that form the logic gate connection between the inputs and output. The code will run a transient analysis over 100ns to simulate the output voltage at node out relative to the input voltages applied at nodes A and B.

Uploaded by

Deepak Kumar Nayak
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
106 views

Nand Layout

The document contains SPICE netlist code that models the behavior of a basic logic gate circuit with 4 transistors. It defines 4 voltage sources to provide inputs to nodes A and B and ground. It also defines the 4 MOSFET transistors that form the logic gate connection between the inputs and output. The code will run a transient analysis over 100ns to simulate the output voltage at node out relative to the input voltages applied at nodes A and B.

Uploaded by

Deepak Kumar Nayak
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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layout2

v (ou t )
8

5
Voltage (V)

-1
0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 00

Time (ns)

layout2
v (B)
5 .0

4 .5

4 .0

3 .5
Voltage (V)

3 .0

2 .5

2 .0

1 .5

1 .0

0 .5

0 .0

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 00

Time (ns)

layout2
v (A)
5 .0

4 .5

4 .0

3 .5
Voltage (V)

3 .0

2 .5

2 .0

1 .5

1 .0

0 .5

0 .0

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 00

Time (ns)

********************************************************************************

* SPICE netlist generated by HiperVerify's NetList Extractor

* Extract Date/Time: Wed Aug 25 16:19:48 2010

* L-Edit Version: L-Edit Win32 13.13.20081106.17:52:26

* Rule Set Name:

* TDB File Name: E:\gunjan 083\Layout2.tdb

* Command File: C:\Documents and Settings\student\My Documents\Tanner


EDA\Tanner Tools v13.1\L-Edit and LVS\Tech\Mosis\morbn20.ext

* Cell Name: Cell0

* Write Flat: YES

********************************************************************************

.include "C:\Documents and Settings\student\My Documents\model files\model_file035.md"

v1 vdd GND 5

v2 A GND PULSE (0 5 0 .1n .1n 20n 40n)

v3 B GND PULSE (0 5 0 .1n .1n 10n 30n)


v4 gnd_ GND 0

.tran 1n 100n

.print tran v(A) v(B) v(out)

M1 1 B gnd_ 2 NMOS l=3.5e-006 w=1.55e-005 ad=1.085e-010 as=1.9375e-010 pd=2.95e-005 ps=5.6e-


005 $(4 12.5 7.5 28)

M2 out A 1 2 NMOS l=5e-006 w=1.55e-005 ad=2.325e-010 as=1.085e-010 pd=6.1e-005 ps=2.95e-005


$(21.5 12.5 26.5 28)

M3 out B vdd 3 PMOS l=3.5e-006 w=9.5e-006 ad=6.65e-011 as=9.5e-011 pd=2.35e-005 ps=3.9e-005 $(4
46.5 7.5 56)

M4 vdd A out 3 PMOS l=4e-006 w=9.5e-006 ad=8.075e-011 as=6.65e-011 pd=3.6e-005 ps=2.35e-005


$(21.5 46.5 25.5 56)

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