Microprocessor 8085 Architecture

3.1 Introduction

Intel 8085 is the most popular 8-bit microprocessor.

It is a 40-pin IC fabricated on a single VLSI chip.
It requires a single +5V power supply. It has in-built clock generation, system control and
interrupt circuitry.
The 8085 P is a programmable digital device which has got a set of instructions designed
internally to manipulate the data and communicate with peripherals.
The internal logic organization or design is called architecture of the P.
It is important to know the architecture because it is the internal architecture of a P which
determines as to what happens to the data inside the P and how and what type of
operations can be performed with the data.

3.2 Block diagram of 8085

To understand the architecture of 8085 P it is necessary to discuss the block diagram. Fig.
3.1 below shows the block diagram of 8085 P. It mainly consists of three sections
(a) Register unit
(b) Arithmetic and logic unit
(c) Timing and control unit
These important sections will be discussed in detail in the subsequent sections.
Register unit
The micro processor 8085 consists of different types of registers
(a) Accumulator
(b) General purpose register
(c) Flag register
(d) Temporary register
(e) Program counter
(f) Stack pointer
Accumulator:
It is an 8-bit register which is used for performing all the arithmetics and logical operations.
Accumulator is also known as register A. During any mathematical or logical operation one
of the operands should be present in the accumulator. The final result is also stored in the
accumulator.

Functional Block diagram

General purpose registers:
There are six 8-bit general purpose registers B, C, D, E, H & L. General purpose registers
are used for temporary storage of data and intermediate results while the processor is
executing the program. Two eight bit registers can be combined for handling 16-bit data.

Combination of two 8-bit registers is known as pair. Valid register pairs are B-C, D-E, H-L.
The H-L pair is used to address memories.
Flag register:
It is an 8-bit register in which five flip flops are used for checking condition. These flip flops
are called flags. Each of these flags can have the value either one or zero to indicate certain
condition after arithmetic and and logical operation. The five flags present in 8085 P are:
(a) Sign flag (b) Zero flag (c) Auxiliary carry flag (d) Parity flag (e) Carry flag
Sign flag (S): After the execution of an arithmetic or logical operation, if bit D 7 of the result
is 1, the sign flag is set. This flag is used with signed numbers and has no relevance for
unsigned numbers. In a given byte, if D7 is 1, the number is said to be negative and if it is
0, the number is considered as positive.
Zero Flag (Z): This flag is set if the result after arithmetic or logical operation turns out to
be zero and is reset if the result is non-zero.
Auxiliary carry (AC): This flag is set if in an arithmetic operation a carry is generated at bit
D3 and passed onto D4. This flag is used internally for BCD operations and is not available to
the user unlike other flags.
Parity (P): After an arithmetic or logical operation, if the result has an even number of 1s,
the flag is set and if there is odd number of 1s the flag is reset.
Carry (CY): If an arithmetic operation results in a carry, the flag is set otherwise it is reset.
It also serves as a borrow flag for subtraction.
The bit position reserved for these flags in the flag register are as follows:
S
D0

A
D1

D2

AC
D3

D4

P
D5

D6

CY
D7

Temporary register:Register W and Z are known as temporary registers. They are used by the P for storing the
data temporarily during execution of a program. They are 8-bit registers and are not
accessible to the user.
Program Counter:
It is a 16-bit register which holds the address of the instructions. Initially it indicates
towards the starting address of the program but after the first instruction is fetched the
program counter automatically gets incremented by one and points towards the next
instruction. This process continues till the end of the program.
Stack pointer:
The stack pointer is a 16-bit register which basically serves two purposes
(a) Points towards the stack memory. Initially it indicates the beginning of the stack
memory. Whenever something is added to the stack, the stack pointer is decremented and
whenever something is removed from the stack the stack pointer is incremented. Hence the
stack pointer always points to the top of the stack.
(b) Stack pointer also points towards the memory location where the P has to go after
attending an interrupt or a subroutine; therefore it acts as a bookmark.
Arithmetic and logic unit:
This is the unit where all the arithmetic operations like addition, subtraction, multiplication
and division and logical operations like AND, OR, Ex-OR, complement, compare etc. are
performed. It includes the accumulator, the temporary register, the arithmetic and logic
circuits and five flags. The temporary registers are used to store data temporarily during an
arithmetic/logical operation. The result is stored in the accumulator and the flags are set or
reset according to the result of the operation.

Timing and control unit:

The timing and control unit generates timing and control signals which are necessary for the
execution of instruction. It controls data flow between CPU and peripherals. It provides
status, control and timing signals which are required for the operation of memory and I/O
devices.

3.3 8085 System Bus

System bus is basically a group of communication lines/wires that are responsible for
transferring information between different units of the device or peripherals. A typical
microprocessor communicates with memory and other devices using three buses: address
bus, data bus and control bus.
Address bus: Address bus is a unidirectional group of 16 lines i.e. bits flow in one direction
from the P to the peripheral devices. The 8085 P with its 16 address lines is capable of
addressing 216=65536 (64K) memory locations.
Data bus: Data bus carries data in binary form, between microprocessor and peripheral
devices as well as memory. It is a group of 8-bits and is bidirectional. Data bus also carries
instructions from memory to the microprocessor. Size of the bus therefore limits the number
of possible instructions. The 8085 P has 246 bit patterns amounting to 74 different
instructions. These 74 different instructions are therefore called its instruction set.
Control bus: The control bus is combination of various single lines that carry control
signals. The control lines are not group of lines like address and data bus but are individual
lines. Microprocessor generates specific control signals for every operation it performs.
The bus system of 8085 is shown in figure 3.2.

Figure 3.2 8085 Bus Structure

3.4 8085 Pin Description

The 8085 P is an 8-bit microprocessor capable of addressing 64K of memory. It is a 40-pin
IC which requires a power supply of +5V and its operating frequency is 3MHz. Fig. 3.3
shows the pin configuration of 8085 P .The pin configuration of 8085 P can be classified
into six groups namely:
High order Address bus
Multiplexed Address/Data bus
Control and status signals
Power supply and frequency signals
Externally initiated signals and
Serial I/O ports

(1) High order address bus:

The address bus is a group of 16-lines generally identified as A0-A15. The address bus is split
into two segments ADO-AD7 and A8-A15 .The buses from ADO-AD7 are low order address
buses and A8-A15 buses are high order address buses.
(2) Multiplexed Address/Data bus:
The data bus is a group of 8-lines used for transfer of data. These lines are bidirectional i.e.
data flows in both the directions from P to peripherals and vice-versa. They are
represented as ADO-AD7 because they serve dual purpose. They are used as low-order
address bus as well as data bus and therefore they are known as multiplexed address/data
bus.
(3) Control and status signals:
This group of signals includes two control signals, three status signals and one special
signal. These signals are as follows:
Control signal: - and are the two control signals which indicate that the data is to be read
from or written into a selected memory or I/O location. Both are active low signals.
Status signal: - , S1 and SO are the three status signals. is used to differentiate between
I/O and memory operations. When it is high it indicates I/O operation and when it is low it
indicates memory operation. S1 and SO are also status signals but are rarely used in small
systems.
Special signal: - ALE (Address Latch Enable) is a special signal used for demultiplexing
address and data bus (ADO-AD7). It is a positive going pulse generated every time a
machine cycle begins and so long as it remains positive it indicates that the bits on ADO-AD7
are address bits.
(4) Power supply and clock frequency:
The power supply required for 8085 P is +5V. As shown in pinout diagram VCC is connected
to +5V and VSS is connected to the ground of the power supply. The P operates on
frequency of 3MHz, therefore an oscillator of frequency 6MHz is connected between pin no.
1 and 2 as the frequency is internally divided by two. CLK (OUT) i.e. Pin no. 37 is used as a
system clock for other devices.
(5) Externally initiated signals:

There are certain operations which can be initiated by external devices (or signals). For
these externally initiated operations there are individual pins assigned on the
microprocessor chip. Interrupts are also considered as externally initiated signal. Here is a
brief explanation of interrupts and other externally initiated signals.
Interrupts: - The 8085 has five interrupt signals that can be used to interrupt a program
execution. These interrupts are
(a) TRAP: The interrupt with highest priority. It is non-maskable and vectored interrupt i.e.
the P has to attend this interrupt immediately.
(b) RST 7.5, RST 6.5, RST 5.5: These are known as Restart interrupts and have lower
priority than TRAP but have higher priority than the INTR interrupt. They are vectored and
maskable interrupts. Among the three the priority order is RST7.5>RST6.5>RST5.5
(c) INTR: It is a general purpose interrupt. It is maskable and non-vectored interrupt and
has the least priority.
Reset: - When RESET pin is activated, the P suspends all the internal operations and the
program counter is cleared. Now the program execution can again begin at the zero
memory address.
Ready: - The Ready signal is used to synchronize slower peripherals with the
microprocessor. If the signal at READY pin is low the microprocessor enters into a wait state.
Hold: - This signal is used by the external devices to request the microprocessor for using
the buses. When this signal is activated the P leaves is control over the buses and makes
them free for the peripherals to use.
: - Interrupt Acknowledge. This signal is used to acknowledge an interrupt.
HLDA: - Hold Acknowledge. This signal is used to acknowledge the HOLD request.
: - This is an active low signal. When it is activated the buses are tristated, the program
counter is cleared and the microprocessor is reset.
RESET OUT: This signal indicates that the microprocessor is being reset. It can be used to
reset other devices also.
(6) Serial I/O Ports:
To send and receive data serially microprocessor has two pins SID and SOD by using
these pins the P can communicate with other P and peripheral devices. In serial
transmission, data bits are sent over a single line, one bit at a time. SID is Serial Input Data
and SOD stands for Serial Output Data.
SID (Input) On execution of the RIM instruction the data on this line is loaded into the
seventh bit of the accumulator.
SOD(output)- When SIM instruction is executed the 7th bit of the accumulator is output on
SOD line.

3.5 Microprocessor operations

The process of data manipulation and communication with peripherals is determined by the
logic design of the microprocessor. This logic design is called architecture. All the operations
of microprocessor can be classified into following types:
(a) Microprocessor initiated operations
(b) Internal operations
(c) Peripheral or externally initiated operations
Microprocessor initiated operations
Microprocessor initiated operations are usually one of the following operations :
(a) Memory read: Reads data from memory.
(b) Memory write: Writes data into the memory.

(c) I/O Read: Accepts data from input devices.

(d) I/O Write: Sends data to output devices
All these operations are initiated by microprocessor and executed by peripheral devices as a
part of communication process between microprocessor and memory or peripheral devices.
To perform these communication operations, the MPU needs to perform following steps
(a) Identify the memory location or the peripheral devices.
(b) Provide synchronization signal i.e. timing signals.
(c) Transfer the binary information (data and instruction).
All these functions are performed with the help of communication lines called system bus.
The details of the three types of buses i.e. Address bus, data bus and control bus have been
discussed in section 3.1.2

Data flow between memory and MPU:

Figure below explains the flow of data between microprocessing unit and memory. First of
all the 16-bit address is placed on the address bus from the program counter. In the figure it
can be seen that the address is 2005H where the data is placed. The higher order address
i.e. 20H is placed on the address bus A8-A15 while the lower order address is placed on the
multiplexed address and data bus ADO-AD7. The lower order address continues to remain on
this address bus so long as ALE (Address Latch Enable) remains positive. Once ALE goes low
it carries data. The control unit sends the signal to indicate what type of operation is to be
performed. Since the data is to be read from the memory therefore it sends to enable the
memory chip. The byte from the memory location is then placed on the data bus i.e. 4F
saved in location 2005H is placed on the data bus and sent to the instruction decoder. The
instruction is decoded and accordingly the task is performed by the ALU i.e. Arithmetic and
logic unit.

Figure: Data flow between memory and MPU

Internal data operations
These are the operations which are internally performed by the microprocessor. They are
classified into five groups:

1)
2)
3)
4)
5)

Store 8-bit data

Perform arithmetic and logical operation
Test for the conditions
Sequence the execution of instructions
Store data temporarily during execution in the R/W memory locations called the stack.

To perform these operations microprocessor requires registers, Arithmetic and logic unit,
buses and control unit.
To store 8-bit data microprocessor has six general purpose registers. During program
execution, these registers are used to store 8- or 16-bit data. The details of these registers
i.e. B, C, D, E, H and L have already been discussed in register unit.
Arithmetic and logical operations are performed in accumulator and the conditions are
tested by the flag register. Program counter is used to sequence the execution of
instructions and stack memory is used for temporary storage of data during execution and
stack pointer is used to address the stack memory.
Peripheral or Externally initiated operations
There are four externally initiated operations, for which individual pins on the
microprocessor chip are assigned. These operations are RESET, READY, HOLD and
INTERRUPT. The details of all these operations have been discussed in section 3.1.2

Timing and control; Interrupts; Stack Memory; Interfacing

devices

One of the very important unit which co-ordinates the interaction between the P
and other devices including memory is timing and control unit; and discuss about
control signals, timing diagrams and how the process of communication is managed
in microprocessor.
Stack memory is a read/write memory which again plays an important role in the
functioning of P.
Interrupts are externally initiated signals with which the external user can ask P to
perform some task other than the one which it is performing and depending on the
priority of the task P has to perform it at that very moment or may even perform it
after sometime.
Interfacing devices are special hardware circuits through which the P connects to
the peripheral devices for e.g. keyboard, printers, display device etc. and the process
through which this connection is made is called interfacing.

4.2 Timing and control operation

Timing and control operations are performed by timing and control unit.
These operations synchronize the process of communication between P and peripheral
devices by generating the control signals necessary for communication for e.g. and signals
which indicate the availability of data on the data bus.
Whenever P has to execute any instruction, the instruction is first received by the
instruction register (8-bit) through A/D (address/data) bus. The instruction is then passed
on to the instruction decoder where it is split, decoded and then passed to the control unit
to generate necessary control signals for its execution. Besides doing this timing and control
unit also checks whether any internal or external interrupt has occurred. If there is any kind
of interrupt request this unit stops the execution of normal sequence of instructions to
respond to it (interrupt) by generating the required control signals.

To execute any instruction P has to pursue the following steps:

1) Identify the memory location from where the instruction is to be fetched
2) Decode the instruction using instruction decoder
3) Perform the function specified by the decoded instruction
All these operations are performed within a given time interval, which is
provided by the clock of the system. With reference to the above mentioned operations
certain terms can be defined. The definitions are as follows
1) Instruction cycle: Time required for completing the execution of an instruction is known
as instruction cycle. The 8085 instruction cycle consists of one to six machines cycles or
operations.
2) Machine cycle: It is the time required for completing a single operation. This operation
can be accessing memory for read/write operation or accessing I/O device. There can be 3
to 6 clock periods or T-states in a machine cycle.
3) T-states or clock cycles/periods (CLK): T-state is equivalent to one clock period It is
the time in which only a subdivision of the operation can be performed. The total number of
T-states determines the size of the machine cycle required to perform an operation.
These three cycles can be represented with the help of a diagram which is shown in Fig.4.1
below.

Fig 4.1 Representation of different cycles

4.2.1 Timing diagrams

A timing diagram of an instruction is a graphical representation of the time taken by the P

to fetch, decode and execute an instruction. The size of the instruction and the frequency of
the P decides the total amount of time taken to execute an instruction. This can be
illustrated with the help of timing diagram. Consider the instruction MVI A, byte. It is
basically a two byte instruction i.e. it requires two memory locations and this instruction can
be written as follows:
Memory
location
2024

Mnemonics

Comments

Hexcode

MVI A

move immediately
8-bit data in register

3E

A
2025

data

data

So far as the timing diagram of this instruction is concerned it consists of two machine
cycles M1opcode fetch and M2memory read. M1 consists of 4 T-states and M2 consists of
3 T-states. Figure 4.2 (a) and (b) show the opcode fetch and memory read machine cycles
respectively.

Figure 4.2 (a) Opcode fetch Machine cycle (M1) for instruction MVI A , byte

Figure 4.2 (b) Memory read Machine cycle (M2) for instruction MVI A, byte
There are certain points that should be remembered while drawing the timing diagrams as
they make it convenient to draw any timing diagram. These points are:
1) In each instruction cycle, there can be one or more than one machine cycles. The first
machine cycle is always Opcode fetch. It can have four to six T-states.
2) The Memory read cycle requires three T-states
3) As is evident in both the figures that the high order address (A8-A15) bus carries high
order address for the first 3 T-states.
4) ALE (Address Latch Enable) is a positive going pulse which is generated every time a
machine cycle begins and remains positive for one T-state.
5) Low order address bus (AD0-AD7) carries low order address so long as ALE is positive.
6) Low order address bus (AD0-AD7) acts as data bus as soon as signal goes low.
7) If the P is interacting with the memory i.e. reading instruction or data from the memory
or writing information into the memory then IO/M is low and if P is interacting with input or
output device than it is high.
Calculation of execution time of Opcode fetch cycle, machine cycle and
instruction cyle:

Let the clock frequency f=5MHz

One T-state= clock period (1/f)=0.2s
Execution time for Opcode fetch = 4 T = 4 0.2s = 0.8 s
Execution time for Memory read = 3 T = 3 0.2s = 0.6 s
Execution time for instruction = 7 T = 7 0.2s = 1.4 s

4.3 Interrupts
An interrupt can be defined as any signal to the P that alters the normal sequence of
execution of a program. The interrupt can be introduced in the P through an instruction
written in the program or it can even be initiated by external device.
Whenever P receives any interrupt its control gets shifted to some other location in order
to execute a set of instructions called service routine which is written at that location. The
P resumes its operation after completing the service routine. The interrupt process in 8085
is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be
set or reset by using software instructions. There exist two types of interrupts:
a) Software interrupts
b) Hardware interrupts

4.3.1 Software interrupts

The instruction set of 8085 includes eight RST (Restart) instructions referred to as software
interrupts. These are one-byte instructions. Each of these instructions allows the transfer of
the program execution to a specific location on page 00H. Therefore RST instructions act like
a vector that points towards different memory locations.Table1 shows the list of different
RST instructions.
Instruction
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7

Hex Code
C7
CF
D7
DF
E7
EF
F7
FF

Vector location
0000H
0008H
0010H
0018H
0020H
0028H
0030H
0038H

We will discuss the functions performed by certain RESTART instructions like RST0, RST1
and RST5. The RST0 instruction service routine is stored in locations between 0000H and
0007H. When this instruction is given the Program Counter (PC) points to the memory
location 0000H and its current address is loaded into the stack pointer. After the service
routine is executed the PC returns back to the address of the next memory location by
popping back the address from the stack pointer. Similarly RST1 service routine is stored in
memory location 0008H to 000FH. In the same way when RST5 is inserted in the program it
transfers the control to memory location 0028H. It is a break point service routine. The
RST5 instruction displays the contents of accumulator and the flags when the A key is
pressed and returns to the calling program when the Zero key is pressed.

4.3.2 Hardware interrupts

There are five hardware interrupts in 8085. They are:
1) INTR
2) RST 5.5
3) RST 6.5

4) RST 7.5
5) TRAP
The interrupts are also classified as:
a) Vectored interrupts: Vectored interrupts are the ones which have some specific memory
locations on page 00H associated with them and the control is automatically transferred to
the respective memory location without any external hardware. Example of vectored
interrupt is RST5.5, RST6.5, RST7.5 and TRAP.
b) Non-vectored interrupts: Non-vectored interrupts are the ones in which user has to
specify the address along with the interrupt where the control is to be transferred. Example
of non-vectored interrupt is INTR.
c) Maskable interrupts: Maskable interrupts are the one which P need not attend
immediately as and when it comes instead P can ask it to wait for some time. Example of
maskable interrupt is RST5.5, RST6.5, RST7.5 and INTR.
d) Non-Maskable interrupts: It is also known as NMI. It is the interrupt which P has to
attend as and when it comes i.e. it cant be ignored or asked to wait. Example of nonmaskable interrupt is TRAP.
Table 2: Order of interrupts and their call locations

INTR: While executing a program, the P checks the INTR line on execution of each
instruction. If the interrupt enable flip-flop is set and INTR is high, the P after executing
the current instruction resets the interrupt enable flip-flop and sends interrupt acknowledge
signal ( INTA). In order to attend any other interrupt the P has to enable interrupt enable
flip-flop again.
With the help of INTR interrupt the user can also extend the interrupt capability of 8085 P.
The interrupt controller device used for this purpose is IC8259, which helps in catering upto
eight peripheral devices.
RST 7.5, RST 6.5, RST 5.5: All the three interrupts are vectored and maskable interrupts.
In order to enable these interrupts the P requires two instructions:
a) EI (Enable Interrupt)
b) SIM (Set Interrupt Mask)
Besides these three interrupts are sensitive to different types of triggering as explained
below:
RST 5.5 and RST 6.5: These are level sensitive interrupts which implies that the triggering
level should be on until the P completes the execution of current instruction. If the P is
not able to respond immediately to these interrupts then they should be stored by external
hardware.
RST 7.5: It is positive-edge sensitive and can be triggered with a short pulse. In this case if
the P is unable to respond immediately then the request is stored internally by D-flip-flop.
TRAP: It is vectored, non-maskable interrupt. It is level-and edge-sensitive, which implies
that the input should go high and remain in that state until it is acknowledged by the P. In

case of TRAP the instructions like EI (Enable interrupt), DI (Disable interrupt) and SIM (Set
Interrupt Mask) are not required i.e. it need not be enabled, and it cannot be disabled. The
triggering of various interrupts can be summarized in the form of diagram as shown below:

Figure 4.3 Triggering levels of various interrupts

4.4 Stack Memory

The stack memory can be described as a set of memory locations in the R/W memory that
are used to store binary information temporarily during the execution of a program. The
stack memory is used by both P and programmer. Whenever P comes across any
interrupt or subroutine the sequence of program execution is altered, in such a situation P
automatically places the address of the memory location present in the program counter on
to the stack and after executing the interrupt or the subroutine the P returns back to the
original program by checking the address present in the stack.
Similarly the contents of the register can be stored on to the stack and retrieved from the
stack by the programmer. During the execution of a program sometimes it becomes
necessary to save the contents of certain registers and data in memory so that the registers
may be used for other operations. After completing these operations the contents saved in
memory can be transferred back to the registers. Memory locations for this purpose are set
aside by the programmer in the beginning. The set of memory locations kept for this
purpose is called stack.
Stack pointer is initialized in the beginning of the program by using the instruction LXI SP.
This instruction loads the stack pointer register with the 16-bit memory address. Any area
of the RAM can be used as stack but to prevent the program from being destroyed by the
stack information, it is a general practice that the beginning of the stack is at the highest
available memory location. The stack memory is based on last in first out principle (LIFO).
The entering of data into the stack is called PUSH operation and retrieving data from the
stack is called POP operation. The stack pointer always holds the address of the stack top.

4.4.1 Stack Instructions

The commands used for writing into the stack memory and reading from it are
PUSH and POP. The details of how these commands work are discussed in the next
section. These instructions that write and read from the stack are called stack
instructions. In these instructions indirect addressing mode is used, because a 16-bit
register called stack pointer (SP) holds the address of the desired memory location.

4.4.2 How data is transferred into stack and retrieved from the stack using
PUSH and POP command?
Suppose register B contains 6AH and register C contains B7H and we want to transfer this
data to register pair DE using stack then first of all we write a short program for this
purpose. Here we are explaining function of each instruction in the program with the help of
diagrams.
Memory
location
3000

Mnemonics

3003

LXI B, 6AB7H

3006

PUSH B

A
B
D
H
SP

LXI SP, 3079H

6AH

Comments
This instruction loads stack pointer register with
3079H indicating to the P that the memory space
from memory location 3078H and moving upwards can
be used as stack for temporary storage.
This instruction loads register pair BC with 6AB7H.
This instruction loads the contents of reg. B i.e. 6AH in
location 3078H and contents of reg.C i.e. B7H in
3077H.

F
C
E
L

B7H

3079H

Contents of Register and stack memory after PUSH instruction is executed

4.5 Interfacing devices

Interfacing devices are basically hardware circuits that are specially designed to connect P
to external or peripheral devices like display unit, keyboard, printer or any other
input/output device. The process through which this connection is made is called interfacing.
There is a need for interfacing device because of difference in the characteristics of
P and peripheral devices. The difference can be in their operational speed as compared to
P or in their logic levels and power levels. The input and output devices are interfaced
using programmable and non-programmable chips. Programmable devices are the ones
which can be programmed by the user according to the requirement while
nonprogrammable devices cant be programmed by the user.
In this chapter we will give a brief idea of some of the commonly used Programmable
Peripheral Interfacing (PPI) devices/chips\ with 8085 microprocessor.
1. 8155/8156: Multi-functional programmable IO interfacing chip:

The Intel 8155 is a 40-pin IC. It contains 256 bytes RAM, two programmable I/O ports and
a timer so it can be used as I/O interfacing chip or as a memory chip or as a timer chip. The
IC 8156 is identical to the chip 8155 except that
8156 accepts active high chip enable (CE) signal and 8155 an active low CE signal. The
main features of 8155/8156 can be summarized as follows:
1) 256-byte static RAM
2) Two 8-bit I/O ports
3) One 6-bit I/O port
4) One 14-bit binary counter/timer
The 8155 chip is specifically designed to be compatible with the 8085 P, because control
signals like , and and special signal like ALE from 8085 can be directly connected to the
device which in turn eliminates the need for generating control signals like , , and , not only
this it even eliminates the requirement of external demultiplexing of the low-order address
bus AD7-AD0.
2. 8255: Programmable Peripheral interfacing chip:
It is programmable, parallel I/O device which is widely used to transfer data under various
conditions. Its advantage is that it is economical when multiple I/O ports are used, it is
flexible and versatile, therefore, it can be used with almost any P. It is a 40-pin IC which
operates on +5V power supply. Its main features can be summarized as follows:
1) Three 8-bit I/O ports constituted by 24-pins of the IC
2) Data bus buffer unit consisting of bidirectional data bus (DO-D7)
3) Read/Write control logic unit consisting of six input control signals (RF, WR,
RESET, CS, Ao and A1).
4) Group A and Group B control logic : The 8255 I/O ports are divided into these two
groups. Each of the control block (Group A and Group B) receives commands from
Read/write control logic and corresponding control word and accordingly controls the I/O
port which comes under its block.
3. 8279: Display/Keyboard interface IC:
The IC 8279 is a programmable display and keyboard controller. This device is well suited
for interfacing of matrix keyboard and seven-segment display in 8085 P based system.
There are two ways of interfacing a device with P (a) hardware approach (b) software
approach. The 8279 is a hardware approach of interfacing. In software approach the
disadvantage is that the P is occupied for a considerable amount of time in refreshing the
display and checking the keyboard which is not the case if hardware approach is used. The
disadvantage of using 8279 is that it is costly but advantage is that it saves processor time
and the software development cost.
The 8279 IC is a 40 pin IC which requires 5V supply. It has got four major sections namely:
1) Keyboard section
2) Scan section
3) Display section
4) Microprocessor unit (MPU) interface
Besides the interfacing devices discussed above there are various other popularly used
devices which are used for the purpose of interfacing and the names of some of them are
mentioned below:
1) 8251: Universal synchronous/asynchronous receiver/transmitter.
2) 8212 : Latch
3) 0801/0802 : Digital to analog converter (DAC)
4) 0808/0809 : Analog to Digital converter (ADC)