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Lect03 Qual Metrics

This document discusses quality metrics for digital designs, focusing on cost, functionality, and robustness. It analyzes the cost of an integrated circuit in terms of fixed costs, variable costs, and their relationship to chip area and die yield. Larger chip sizes result in lower die yields and higher costs. Functionality and robustness are measured by noise margins and the regenerative property of gates. Noise margins indicate a gate's sensitivity to noise sources, while regenerative gates can withstand accumulated noise. Noise immunity depends on suppressing both internal noise sources proportional to signal swing, and external fixed noise sources.

Uploaded by

Kumar Ganesh
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
15K views

Lect03 Qual Metrics

This document discusses quality metrics for digital designs, focusing on cost, functionality, and robustness. It analyzes the cost of an integrated circuit in terms of fixed costs, variable costs, and their relationship to chip area and die yield. Larger chip sizes result in lower die yields and higher costs. Functionality and robustness are measured by noise margins and the regenerative property of gates. Noise margins indicate a gate's sensitivity to noise sources, while regenerative gates can withstand accumulated noise. Noise immunity depends on suppressing both internal noise sources proportional to signal swing, and external fixed noise sources.

Uploaded by

Kumar Ganesh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Basic Properties of a Digital Design


These help quantify the quality of a design from different perspectives:
Cost
Functionality
Robustness
Performance
Energy consumption
Which of these criteria is important is dependent on the application:
Performance is important for compute servers.
Energy consumption is a dominant metric for cell-phones.
The following analysis focuses on the quality metrics of a simple inverter.
These carry forward to the analysis of more complex entities discussed later.
Before doing so, let's consider the cost of an integrated circuit.

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Cost of an Integrated Circuit


Total cost of a product can be broken down into two basic components:
Recurring expenses (variable cost).
Non-recurring expenses (fixed cost).
Fixed cost is Independent of sales volume.
Includes effort in time and manpower it takes to produce the design.
Indirect costs (company overhead that cannot be billed directly to one product), e.g.,
R&D, manufacturing equipment, marketing, etc.
Variable cost accounts for cost directly attributable to a manufactured product.
It is proportional to the product volume and includes:
Material cost
Assembly cost
Testing cost
Total cost:
cost/IC = variable cost per IC + (fixed cost/volume)
2

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Cost of an Integrated Circuit


The impact of fixed cost is more pronounced for small-volume products.
The design of a microprocessor can afford to support a large design team.
The cost to produce a transistor has dropped exponentially over the past decades.
However, the form of the equation for variable cost has not changed:
Cost of die + Cost of die test + Cost of packagingVariable cost = ---------------------------------------------------------------------------------------------------------------------Final test yield
Cost of wafer
Cost of die = -----------------------------------------------------Dies/wafer Die yield
We will focus on the cost of the die in this analysis.
It's clear that Cost of die is related to chip area.
The bigger the die, the more it costs since Dies/wafer gets smaller.

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Cost of an Integrated Circuit


The actual relation between cost and area is more complex and depends on die yield.
Die yield is related to the number of defects, the size of the die and the complexity of the
manufacturing process.
Under the assumptions that:
Defects are randomly distributed over the wafer.
Yield is inversely proportional to the complexity of the fabrication process.
Die yield can be expressed as:

Defects
per
unit
area

Die
size

Die yield = 1 + --------------------------------------------------------------------------

is related to the number of masks, a measure of process complexity.


It is approximately 3.0 today.
Defects per unit area depends heavily on the maturity of the process but the range 0.5 to
1.0 per cm2 is typical.
4

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Cost of an Integrated Circuit


For example, assume:
Wafer size is 12 inches
Die size is 2.5 cm2
1 defects/cm2
is 3
What is the die yield?
Dies per wafer (which takes into account the dies lost along the perimeter):
2

( wafer diameter 2 )
wafer diameter
Dies/wafer = ------------------------------------------------------------ --------------------------------------------die area
2 die area
Plugging in yields 252 (=296 - 44) potentially operational die.
Plugging in for die yield gives 16%!
Therefore, on average, only 40 dies will be functional.

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Cost of an Integrated Circuit


The bottom line:
The number of good dies/wafer = dies/wafer * die yield.
The larger and/or more complex the chip, the more costly -- its not a linear relationship.
Cost of die = f ( die area )

for = 3.0

The designer is going to be interested in using smaller gates, for two reasons:
They reduce die size.
Smaller gates tend to be faster and consume less energy.
Total gate capacitance (a dominant performance parameter) often scales with area.
The # of transistors in a gate is often indicative of implementation area, although complex
interconnect can cause wiring area to dominate.

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Functionality and Robustness


Measured behavior of a manufactured gate normally deviates from the expected response
because:
Variations in manufacturing process (process variations)
Dimensions, threshold voltage and currents of a MOS transistor can vary significantly between runs, between wafers, and within chips.
Noise sources
Unwanted variations of voltages and currents at the logic nodes.

Inductive coupling

Capacitive coupling

Power and Ground Noise.

Most noise sources are internal and proportional to the logic swing while external
noise source amplitudes are not related to signal levels.
Coping with these is a major challenge in high performance circuit design.
7

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Functionality and Robustness


Steady-state parameters of a gate (static behavior) determine how robust it is to manufacturing and noise variations.
Their analysis requires an understanding of how digital signals are represented in electronic
circuits.
The transformation of an electrical voltage into a discrete variable (logic value abstraction)
is accomplished via the definition of nominal voltage levels.
VOH: High logic level.
VOL: Low logic level.
The difference between VOH and VOL is called the logic or signal swing, Vsw.
The electrical function of a gate is expressed by its voltage-transfer characteristic (VTC)
or DC transfer characteristic.

Quality Metrics of a Digial Design

Advanced VLSI Design

CMPE 640

Functionality and Robustness


VTC for an inverter.
A graph that plots output voltage as a function of the input voltage:
Vout = f(Vin).
VOH
Vout

VOL

slope = -1
f

VOH = f(VOL)

"1"

VIH

Vin=Vout
VM (gate threshold voltage)
slope = -1

VOL VIL VIH


Undefined region

VOH

VOL = f(VOH)

"0"

NMH

Undefined
region
VIL
NML
VOL

VOH Vin
voltage -> logic

Even when an ideal input signal is applied to the input, the output often deviates from
the ideal, due to noise and output loading.
9

Quality Metrics of a Digial Design

Advanced VLSI Design

CMPE 640

Functionality and Robustness


Large 1 and 0 intervals are desirable.
A measure of the sensitivity of a gate to noise is given by noise margins:
NML (noise margin low) = VIL - VOL
NMH (noise margin high) = VOH - VIH
"1"

VOH

NMH

VIH
Undefined
region
VIL

NML

VOL
"0"
Gate
output
Stage M

Gate
input
Stage M + 1

10

Quality Metrics of a Digial Design

Advanced VLSI Design

CMPE 640

Functionality and Robustness


For example:
VIL = 0.8

VDD

Vin

Vout

0.9V

Vout
Vin

0.9V

VIH = 1.3 VDD

Assume output nominal voltages are:


VOH = 1.7V
VOL = 0.1V
NML = VIL - VOL = 0.8 - 0.1 = 700mV
NMH = VOH - VIH = 1.7 - 1.3 = 400mV
11

Quality Metrics of a Digial Design

Advanced VLSI Design

CMPE 640

Functionality and Robustness


Regenerative Property:
Large noise margins are desirable but not a sufficient requirement.
The gate must also possess the regenerative property.
It's regenerative if the accumulation of additional noise sources does not drive the signal into the undefined region.
out

out
f(v)

v1

finv(v)

v1
finv(v)

Two stable
operating
points
v2

v0

Regenerative

in

One stable
operating
point

f(v)

in
v0 v2
Nonregenerative

Regenerative requires that the |gain| be greater than 1 in the transient (undefined)
region, bordered by regions with gains less than 1.
Points VIH and VIL define the borders.
12

Advanced VLSI Design

Quality Metrics of a Digial Design

CMPE 640

Functionality and Robustness


Noise immunity
Noise margins expresses the capability of a circuit to overpower a noise source.
Noise immunity expresses the ability of a system to process and transmit information
correctly in the presence of noise.
Many digital circuits with low noise margins have good noise immunity because the
reject a noise source rather than overpower it.
These circuits allow only a small fraction of the noise source to couple to important circuit nodes.
Noise sources, as mentioned, are divided into:
Sources proportional to the logic swing, Vsw:
Impact on signal node is gVsw.
Sources that are fixed:
Impact on signal node is fVNf with VNf is the amplitude of noise source and f is
transfer function from noise source to signal node.

13

Quality Metrics of a Digial Design

Advanced VLSI Design

CMPE 640

Functionality and Robustness


Noise immunity
Assume the noise margins are half the voltage swing.
For correct operation, the noise margins have to be larger than the sum of the noise
values:
V NM

V sw
= --------- f i V Nfi + g j V sw
2
i

Therefore, the minimum signal swing necessary of system operation is:


2 f i V Nfi
i
V sw --------------------------1 ( 2 ) gj
j

The signal swing (and noise margin) has to be large enough to overpower the fixed
sources, fiVNfi.
However, increasing Vsw does not work for internal sources.
Here, gj must be small. (The impact of the internal sources is dependent upon the
noise suppressing capabilities of the gate).
14

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