Digital Design Using Verilog

www.jntuworld.com

www.jntuworldupdates.org

always @(posedge clk) begin

assign pcinc = pc + 4;

ter
gis
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c
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irq
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If (done) $finish;

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+4

6>
0:1
: <2
Ra
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en
dm
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PC

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for (i=0; i < 31; i = i+1) begin

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Figures by MIT OCW.

6.884 Spring 2005

02/04/05

L02 Verilog 1

Hardware Description Languages

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www.jntuworldupdates.org

In the beginning designs involved just a few

gates, and thus it was possible to verify these

circuits on paper or with breadboards

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2
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L02 Verilog 2

Hardware Description Languages

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www.jntuworldupdates.org

As designs grew larger and more complex, designers

began using gate-level models described in a
Hardware Description Language to help with
verification before fabrication
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L02 Verilog 3

Hardware Description Languages

When designers began working

on 100,000 gate designs, these
gate-level models were too lowlevel for the initial functional
specification and early highlevel design exploration

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L02 Verilog 4

Hardware Description Languages

Designers again turned to HDLs

for help abstract behavioral
models written in an HDL
provided both a precise
specification and a framework
for design exploration

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L02 Verilog 5

Allows designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

www.jntuworld.com

Advantages of HDLs

www.jntuworldupdates.org

HDLs do this with

modules and interfaces

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6
Figure by MIT OCW.
02/04/05

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L02 Verilog 6

Allows designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

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Advantages of HDLs

www.jntuworldupdates.org

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L02 Verilog 7

Allows designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

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Advantages of HDLs

www.jntuworldupdates.org

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L02 Verilog 8

Allows designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction
Processor
A

Processor
B

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Advantages of HDLs

www.jntuworldupdates.org

Processor
C

Network

Memory
Bank
A
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Memory
Bank
B
9
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L02 Verilog 9

Allows designers to talk about what the hardware

should do without actually designing the hardware
itself, or in other words HDLs allow designers to
separate behavior from implementation at various
levels of abstraction

www.jntuworld.com

Advantages of HDLs

www.jntuworldupdates.org

Designers can develop an executable functional specification

that documents the exact behavior of all the components and
their interfaces
Designers can make decisions about cost, performance,

power, and area earlier in the design process

Designers can create tools which automatically manipulate

the design for verification, synthesis, optimization, etc.

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L02 Verilog 10

VHDL

Verilog

ADA-like verbose syntax, lots

of redundancy

C-like concise syntax

Extensible types and

simulation engine

Built-in types and logic

representations

Design is composed of entities

each of which can have
multiple architectures

Design is composed of modules

which have just one
implementation

Gate-level, dataflow, and

behavioral modeling.
Synthesizable subset.

Gate-level, dataflow, and

behavioral modeling.
Synthesizable subset.

Harder to learn and use, DoD

mandate

Easy to learn and use, fast

simulation

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A Tale of Two HDLs

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L02 Verilog 11

Advantages

www.jntuworld.com

We will use Verilog

www.jntuworldupdates.org

Choice of many US design teams

Most of us are familiar with C-like syntax
Simple module/port syntax is familiar way to organize
hierarchical building blocks and manage complexity
With care it is well-suited for both verification
and synthesis

Disadvantages
Some comma gotchas which catch beginners everytime
C syntax can cause beginners to assume C semantics
Easy to create very ugly code, good and consistent
coding style is essential

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L02 Verilog 12

An HDL is NOT a

Software Programming Language

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Software Programming Language

Language which can be translated into machine instructions

and then executed on a computer

Hardware Description Language

Language with syntactic and semantic support for modeling the

temporal behavior and spatial structure of hardware
module foo(clk,xi,yi,done);
input [15:0] xi,yi;
output done;
always @(posedge clk)
begin:
if (!done) begin
if (x == y) cd <= x;
else (x > y) x <= x - y;
end
end
endmodule

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L02 Verilog 13

Hierarchical Modeling with Verilog

A Verilog module includes a module name and an

interface in the form of a port list

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Must specify direction and bitwidth for each port

module adder( A, B, cout, sum );

input [3:0] A, B;
output
cout;
output [3:0] sum;

adder
cout

// HDL modeling of
// adder functionality

sum
endmodule
Don't forget the semicolon!

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L02 Verilog 14

Hierarchical Modeling with Verilog

A Verilog module includes a module name and an

interface in the form of a port list

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www.jntuworldupdates.org

Must specify direction and bitwidth for each port

Verilog-2001 introduced a succinct ANSI C style portlist

module adder( input [3:0] A, B,

output
cout,
output [3:0] sum );
// HDL modeling of 4 bit
// adder functionality

adder
cout

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sum

endmodule

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L02 Verilog 15

Hierarchical Modeling with Verilog

A module can contain other modules through

module instantiation creating a module hierarchy

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Modules are connected together with nets

Ports are attached to nets either by position or by name

b
cin

cout

module FA( input a, b, cin

output cout, sum );
// HDL modeling of 1 bit
// adder functionality

FA

endmodule

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L02 Verilog 16

Hierarchical Modeling with Verilog

A module can contain other modules through

module instantiation creating a module hierarchy

www.jntuworld.com

www.jntuworldupdates.org

Modules are connected together with nets

Ports are attached to nets either by position or by name
A

module adder( input [3:0] A, B,

output
cout,
output [3:0] S );

adder
cout

FA

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FA

FA

FA
FA
FA
FA
FA

fa0(
fa1(
fa2(
fa3(

...
...
...
...

);
);
);
);

endmodule

17
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L02 Verilog 17

Hierarchical Modeling with Verilog

A module can contain other modules through

module instantiation creating a module hierarchy

www.jntuworld.com

www.jntuworldupdates.org

Modules are connected together with nets

Ports are attached to nets either by position
A

module adder( input [3:0] A, B,

output
cout,
output [3:0] S );

adder
cout

FA

FA

FA

wire c0, c1, c2;

FA fa0( A[0], B[0],

FA fa1( A[1], B[1],
FA fa2( A[2], B[2],
FA fa3( A[3], B[3],

6.884 Spring 2005

c0, S[0] );

c1, S[1] );

c2, S[2] );

cout, S[3] );

FA
endmodule

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0,
c0,
c1,
c2,

18
02/04/05

Carry Chain
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L02 Verilog 18

Hierarchical Modeling with Verilog

A module can contain other modules through

module instantiation creating a module hierarchy

www.jntuworld.com

www.jntuworldupdates.org

Modules are connected together with nets

Ports are attached to nets either by position or by name
A

module adder( input [3:0] A, B,

output
cout,
output [3:0] S );

adder
cout

FA

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FA

FA

wire c0, c1, c2;

FA fa0( .a(A[0]), .b(B[0]),
.cin(0), .cout(c0),
.sum(S[0] );
FA

FA fa1( .a(A[1]), .b(B[1]),

...
endmodule
19
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L02 Verilog 19

Data Values

Numeric Literals

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Verilog Basics

www.jntuworldupdates.org

4b10_11
0 1
X Z

Underscores
are ignored
Base format
(d,b,o,h)
Decimal number
representing size in bits

32h8XXX_XXA3

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L02 Verilog 20

3 Common Abstraction Levels

Behavioral

Modules high-level algorithm is

implemented with little concern
for the actual hardware

Dataflow

Module is implemented by
specifying how data flows
between registers

Gate-Level

Module is implemented in terms

of concrete logic gates (AND,
OR, NOT) and their
interconnections

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L02 Verilog 21

3 Common Abstraction Levels

Behavioral

Designers can create

lower-level models from
the higher-level models
either manually or
automatically

Dataflow

The process of
automatically generating a
gate-level model from
either a dataflow or a
behavioral model is called

Gate-Level
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Logic Synthesis

22
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L02 Verilog 22

Gate-Level : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

Basic logic gates are built-in

primitives meaning there is no
need to define a module for
these gates

wire [1:0] sel_b;

not not0( sel_b[0], sel[0] );

not not1( sel_b[1], sel[1] );

wire n0, n1, n2,

and and0( n0, c,
and and1( n1, a,
and and2( n2, d,
and and3( n3, b,

n3;

sel[1]
sel_b[1]
sel[1]
sel_b[1]

);

);
);

);

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sel[0]

sel[1]

wire x0, x1;

nor nor0( x0, n0, n1 );

nor nor1( x1, n2, n3 );

wire y0, y1;

or or0( y0, x0, sel[0]
);
or or1( y1, x1, sel_b[0] );

out

d
b

nand nand0( out, y0, y1 );

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endmodule
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L02 Verilog 23

Dataflow : 4-input Multiplexer

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module mux4( input a, b, c, d

input [1:0] sel,
output out );
wire out, t0, t1;

assign t0 = ~( (sel[1] & c) | (~sel[1] & a) );

assign t1 = ~( (sel[1] & d) | (~sel[1] & b) );

assign out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );

endmodule

This is called a continuous assignment

since the RHS is always being evaluated
and the result is continuously being
driven onto the net on the LHS
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L02 Verilog 24

Dataflow : 4-input Multiplexer

www.jntuworld.com

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module mux4( input a, b, c, d

input [1:0] sel,
output out );
wire t0 = ~( (sel[1] & c) | (~sel[1] & a) );
wire t1 = ~( (sel[1] & d) | (~sel[1] & b) );
wire out = ~( (t0 | sel[0]) & (t1 | ~sel[0]) );
endmodule

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An implicit continuous assignment combines

the net declaration with an assign statement
and thus is more succinct

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L02 Verilog 25

Dataflow : 4-input Mux and Adder

// Four input muxltiplexor

module mux4( input a, b, c, d
input [1:0] sel,
output out );
assign out = (
(
(
(

sel
sel
sel
sel

==
==
==
==

0
1
2
3

)
)
)
)

?
?
?
?

a
b
c
d

:
:
:
: 1bx;

Dataflow style Verilog

enables descriptions
which are more
abstract than gatelevel Verilog

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endmodule
// Simple four bit adder
module adder( input [3:0] op1, op2,
output [3:0] sum );
assign sum = op1 + op2;
endmodule

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L02 Verilog 26

Dataflow modeling enables the designer to focus

on where the state is in the design and how the
data flows between these state elements without
becoming bogged down in gate-level details

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Dataflow : Key Points

www.jntuworldupdates.org

Continuous assignments are used to connect

combinational logic to nets and ports

A wide variety of operators are available including:

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Arithmetic:
Logical:
Relational:
Equality:
Bitwise:
Reduction:
Shift:
Concatenation:
Conditional:

+ - * / % **

! && ||
> < >= <=
== != === !===
~ & | ^ ^~
& ~& | ~| ^ ^~

>> << >>> <<<

{ }

?:

27

02/04/05

Avoid these

operators since

they usually

synthesize poorly

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L02 Verilog 27

Dataflow modeling enables the designer to focus

on where the state is in the design and how the
data flows between these state elements without
becoming bogged down in gate-level details

www.jntuworld.com

Dataflow : Key Points

www.jntuworldupdates.org

Continuous assignments are used to connect

combinational logic to nets and ports

A wide variety of operators are available including:

www.specworld.in
6.884 Spring 2005

Arithmetic:
Logical:
Relational:
Equality:
Bitwise:

Reduction:

Shift:

Concatenation:
Conditional:

+ - * / % **

! && ||

> < >= <=

== != === !===
~ & | ^ ^~
& ~& | ~| ^ ^~
>> << >>> <<<
{ }

?:
28

02/04/05

assign signal[3:0]

= { a, b, 2b00 }

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L02 Verilog 28

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

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reg out;
always @( a or b or c or d or sel )

begin

if ( sel == 0 )

An always block is a behavioral

out = a;
block which contains a list of
else if ( sel == 1 )
expressions which are (usually)
out = b

evaluated sequentially
else if ( sel == 2 )

out = c
The code in an always block can
else if ( sel == 3 )

be very abstract (similar to C

out = d

end
code) here we implement a mux

with an if/else statement

endmodule
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L02 Verilog 29

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

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reg out;
always @( a or b or c or d or sel )
begin
if ( sel == 0 )
out = a;
else if ( sel == 1 )
An always block can include a
out = b
sensitivity list if any of these
else if ( sel == 2 )

signals change then the always

out = c

else if ( sel == 3 )

block is executed
out = d

end
endmodule
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L02 Verilog 30

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

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reg out;
always @( a, b,
begin
if ( sel == 0
out = a;
else if ( sel
out = b
else if ( sel
out = c
else if ( sel
out = d
end

c, d, sel )
)
== 1 )

In Verilog-2001 we can use a

comma instead of the or

== 2 )
== 3 )

endmodule
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L02 Verilog 31

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

www.jntuworld.com

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What happens if we accidentally

leave off a signal on the
always @( a, b, c, d, sel )
sensitivity list?
reg out;

begin
if ( sel == 0
out = a;
else if ( sel
out = b
else if ( sel
out = c
else if ( sel
out = d
end

)
== 1 )
== 2 )

The always block will not

execute if just d changes so if
sel == 3 and d changes then
out will not be updated

== 3 )

This will cause discrepancies

between simulated and
synthesized hardware there
are no sensitivity lists in real
hardware so it would work fine!

endmodule
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L02 Verilog 32

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

www.jntuworld.com

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reg out;
always @( * )
begin
if ( sel == 0
out = a;
else if ( sel
out = b
else if ( sel
out = c
else if ( sel
out = d
end

)
== 1 )

In Verilog-2001 we can use the

@(*) construct which creates a
sensitivity list for all signals
read in the always block

== 2 )
== 3 )

endmodule
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L02 Verilog 33

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

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reg out;
always @( * )

begin

case ( sel )

0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase

end

Always blocks can contain case

statements, for loops, while loops,
even functions they enable
high-level behavioral modeling

endmodule

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L02 Verilog 34

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );
reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase

end

What about this funny

reg statement?
Is this how you create
a register in Verilog?

www.jntuworld.com

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No! and whoever

decided on the reg
syntax really
messed things up!

endmodule

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Figure by MIT OCW.

L02 Verilog 35

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );
reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase
end
endmodule

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In Verilog a reg is just a variable

when you see reg think variable not
hardware register!
Any assignments in an always block
must assign to a reg variable the
reg variable may or may not actually
represent a hardware register
If the always block assigns a value to
the reg variable for all possible
executions then the reg variable is
not actually a hardware register
36
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L02 Verilog 36

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

www.jntuworld.com

www.jntuworldupdates.org

What about in this

situation? Will the
generated hardware
include a latch for out?

reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase

end

endmodule

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Figure by MIT
OCW.
L02 Verilog 37

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

www.jntuworld.com

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Maybe! What if sel == xx?

Then out is unassigned and
the hardware must maintain
the previous value of out!

reg out;
always @( * )
begin
case ( sel )
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase

end

endmodule

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L02 Verilog 38

Behavioral : 4-input Multiplexer

module mux4( input a, b, c, d

input [1:0] sel,
output out );

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Fix it with a default clause

in the case statement
then no hardware latch is
inferred

reg out;
always @( * )
begin
case ( sel )
default : out = 1bx;
0 : out = a;
1 : out = b;
2 : out = c;
3 : out = d;
endcase

end

endmodule

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Figure by MIT
OCW.
L02 Verilog 39

Behavioral Non-Blocking Assignments

always @( posedge clk )

begin
x = next_x;
end
next_x

always @( posedge clk )

begin
x <= next_x;
end
next_x

clk

always @( posedge clk )

begin
x <= next_x;
y <= x;
end

next_x

clk

clk

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clk

always @( posedge clk )

begin
x = next_x;
y = x;
end
next_x

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clk

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L02 Verilog 40

Behavioral Non-Blocking Assignments

always @( posedge clk )

begin
y <= x;
x <= y;
end

always @( posedge clk )

begin
y = x;
x = y;
end
X

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clk

Take Away Point - always ask

yourself Do I need blocking or
non-blocking assignments for this
always block?

clk

Never mix and match!

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L02 Verilog 41

Which abstraction is the right one?

Designers usually use a mix of all three! Early on in

the design process they might use mostly behavioral

models. As the design is refined, the behavioral

models begin to be replaced by dataflow models.

Finally, the designers use automatic tools to

synthesize a low-level gate-level model.

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Behaviora
l

Dataflow
G at
e-L
eve
l
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L02 Verilog 42

Revisiting Logic Synthesis

Behavioral

Modern tools are able to

synthesize more and more
behavioral Verilog code
directly to the gate-level

Dataflow

The problem though, is

that it is very hard to
predict what the generated
hardware will look like
This makes it difficult to
perform rational design
space exploration

Gate-Level
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L02 Verilog 43

Revisiting Logic Synthesis

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In this course we will

mostly stick to very
predictable dataflow to
gate-level synthesis we
want to have a good idea
what kind of hardware we
are generating!

Behavioral
Dataflow
Gate-Level
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L02 Verilog 44

Writing Parameterized Models

module mux4 #( parameter width )

( input [width-1:0] a, b, c, d
input [1:0] sel,
output [width-1:0] out );

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...
endmodule
// Specify parameters at instantiation time
mux4 #( .width(32) )
alu_mux( .a(op1), .b(bypass), .c(32b0), .d(32b1),
.sel(alu_mux_sel), .out(alu_mux_out) );

Parameters enable static configuration of modules at

instantiation time and can greatly increase the
usefulness of your modules
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L02 Verilog 45

Writing Parameterized Models

module adder #( parameter width )

( input [width-1:0] op1,op2,
output cout,
output [width-1:0] sum );

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wire [width-1:0] carry;

assign carry[0] = 0;
assign cout = carry[width]
genvar i;
generate
for ( i = 0; i < width; i = i+1 )
begin : ripple
FA fa( op1[i], op2[i],

carry[i], carry[i+1] );

end

endgenerate

Generate blocks can

use parameters to
instantiate a variable
number of sub-modules
or to create a variable
number of nets

endmodule
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L02 Verilog 46

www.jntuworld.com

Static Elaboration

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Model
Static Elaboration

Elaborated Model
Synthesis

Gate-Level
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L02 Verilog 47

Lets briefly examine two larger digital designs

and consider the best way to model

these designs in Verilog

GCD
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Larger Examples

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Beta
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L02 Verilog 48

GCD Behavioral Example

module gcd_behavioral #( parameter width = 16 )

( input [width-1:0] A_in, B_in,
output [width-1:0] Y );

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reg [width-1:0] A, B, Y, swap;

integer
done;

always @( A_in or B_in )

begin

done = 0;

A = A_in; B = B_in;

while ( !done )
begin
if ( A < B )

begin

swap = A;

A = B;

B = swap;
end
else if ( B != 0 )

A = A - B;

else
done = 1;
end

We write the general

algorithm in an always block
using a very C-like syntax

Y = A;
end
endmodule
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L02 Verilog 49

GCD Behavioral
Test Harness

module gcd_test;
parameter width = 16;
reg [width-1:0] A_in, B_in;
wire [width-1:0] Y;

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gcd_behavioral #( .width(width) )

gcd_unit( .A_in(A_in), .B_in(B_in), .Y(Y) );

initial

begin

// Default inputs if cmdline args

// are not provided
A_in = 27;

B_in = 15;

// Read in cmdline args

$value$plusargs("a-in=%d",A_in);
$value$plusargs("b-in=%d",B_in);
// Let the simulation run
#10;
// Output the results
$display(" a-in
= %d", A_in );
$display(" b-in
= %d", B_in );
);
$display(" gcd-out = %d", Y
$finish;
end

We use a test harness to drive

the GCD module. The test
harness includes an initial block,
which is similar to always block
except it executes only once at
time = 0.
Special directives which begin
with $ enable the test harness
to read command line arguments,
use file IO, print to the screen,
and stop the simulation

endmodule
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L02 Verilog 50

go

done

Control Unit

zero?

lt

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GCD RTL Example

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out

A_in

sub

B_in

Design
Design Strategy
Strategy
Partition
Partition into
into control
control and
and datapath
datapath
Keep
Keep all
all functional
functional code
code in
in the
the leaf
leaf modules
modules
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L02 Verilog 51

module gcd_dpath #( parameter width = 16 )

( input clock,
input A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel,
input [width-1:0] A_in, B_in,
output B_zero, A_lt_B,
output [width-1:0] Y );

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GCD RTL Datapath

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reg [width-1:0] A, B;

assign Y = A;

// Datapath logic
wire [width-1:0] out
= ( out_mux_sel ) ? B : A - B;

wire [width-1:0] A_next = ( A_mux_sel ) ? out : A_in;

wire [width-1:0] B_next = ( B_mux_sel ) ? A : B_in;

// Generate output control signals

wire B_zero = ( B == 0 );
wire A_lt_B = ( A < B );
// Edge-triggered flip-flops
always @( posedge clock )
begin

if ( A_en )
A <= A_next;

if ( B_en )

B <= B_next;

end

Edge-triggered

flip-flops with

enables

A mix of dataflow
and behavioral

endmodule
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L02 Verilog 52

GCD RTL Control Unit

module gcd_ctrl ( input

input
output
output

clock, reset, go,

B_zero, A_lt_B,
A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel,
done );

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// The running bit is one after go goes high and until done goes high
reg running = 0;

always @( posedge clock )

begin

if ( go )
running <= 1;

else if ( done ) running <= 0;

end

// Combinational control logic - we group all the control signals

// onto one bus to make the Verilog more concise

reg [5:0] ctrl_sig;

assign { A_en, B_en, A_mux_sel, B_mux_sel, out_mux_sel, done } = ctrl_sig;

always
begin
if (
else
else
else
end

@(*)

!running )
if ( A_lt_B )
if ( !B_zero )

ctrl_sig
ctrl_sig
ctrl_sig
ctrl_sig

=
=
=
=

6'b11_00x_0;
6'b11_111_0;
6'b10_1x0_0;
6'b00_xxx_1;

//
//
//
//

Latch in A and B values

A <= B and B <= A
A <= A - B and B <= B
Done

endmodule
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L02 Verilog 53

We use the same test inputs to test both the

behavioral and the RTL models. If both models
have the exact same observable behavior then the
RTL model has met the functional specification.

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GCD Testing

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Test Inputs

Behavioral
Model

RTL
Model

Identical
Outputs?
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L02 Verilog 54

Beta Redux

I thought I already did

6.004

ILL

XAdr OP JT

PCSEL

PC

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00

+4

Instruction

Memory

Ra: <20:16>

RA2SEL

WASEL
XP

Rc: <25:21>

RA1

WA
WA

RD1

PC+4+4*SXT(C)
IRQ

Rc: <25:21>

Rb: <15:11>

Register
File

RA2
WD
RD2

WE

WERF

Figure by MIT OCW.

JT

C: SXT(<15:0>)

Z
ASEL

BSEL

Control Logic
PCSEL
RA2SEL
ASEL

ALU

ALUFN

WD

BSEL
WDSEL
ALUFN
Wr
WERF
WASEL

6.884 Spring 2005

Wr

Data Memory
Adr

RD

PC+4
0 1 2

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R/W

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WDSEL

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L02 Verilog 55

Goals for the Beta Verilog Description

Readable, correct code that clearly

captures the architecture diagram correct by inspection

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Partition the design into regions appropriate for different

implementation strategies. Big issue: wires are bad since they
take up area and have capacitance (impacting speed and power).
Memories: very dense layouts, structured wires pretty much route

themselves, just a few base cells to design & verify.

Datapaths: each cell contains necessary wiring, so replicating cells (for N

bits of datapath) also replicates wiring. Data flows between columnar
functional units on horizontal busses and control flows vertically.
Random Logic: interconnect is random but library of cells can be

designed ahead of time and characterized.

Think about physical partition since wires that cross boundaries can take
lots of area and blocks have to fit into the floorplan without wasteful
gaps.
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L02 Verilog 56

Hey! What happened to abstraction?

Because life is short! If you

have the luxury of writing two
models (the first to experiment
with function, the second to
describe the actual partition you
want to have), by all means! But
with a little experience you can
tackle both problems at once.

Wasnt the plan to

abstract-away the physical

details so we could

concentrate on getting the

functionality right? Why

are we worrying about wires

and floorplans at this stage?

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Figure by MIT OCW.

L02 Verilog 57

Divide and Conquer

ILL
XAdr OP

PCSEL

JT
2

Step 1: identify memories

Step 2: identify datapaths
Whats left is random logic

1
PC

00

Instruction
Memory
D

+4

Ra: <20:16>

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RA2SEL

WASEL
XP

PC

Rc: <25:21>

RA1

WA
WA

RD1

PC+4+4*SXT(C)
IRQ

Rc: <25:21>

Rb: <15:11>

Register
File

RA2
WD
RD2

WE

1
WERF

JT

C: SXT(<15:0>)

Z
ASEL

BSEL

Control Logic
PCSEL
RA2SEL
ASEL

ALU

ALUFN

WD

BSEL
WDSEL
ALUFN
Wr
WERF

6.884 Spring 2005

Main Datapath

Wr

Data Memory
Adr

WASEL

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R/W

PC+4

0 1 2

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RD

WDSEL

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L02 Verilog 58

Hardware description languages are an essential

part of modern digital design

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Take Away Points

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HDLs can provide an executable functional specification

HDLs enable design space exploration early in design process
HDLs encourage the development of automated tools
HDLs help manage complexity inherent in modern designs

Verilog is not a software programming language so

always be aware of how your Verilog code will map
into real hardware
Carefully plan your module hierarchy since this will
influence many other parts of your design
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L02 Verilog 59

You will be building an RTL model of a

two-stage MIPS processor

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Laboratory 1

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1. Read through the lab and the SMIPS processor

spec which is posted on the labs section
2. Look over the Beta Verilog posted on the MIT server

3. Try out the GCD Verilog example

(or on any MIT server/Linux machine)
% setup 6.884

% cp r /mit/6.884/examples/gcd .

% cat gcd/README

4. Next weeks tutorial will review the Beta

implementation and describe how to use Lab 1
toolchain (vcs, virsim, smips-gcc)

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L02 Verilog 60