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Chapter 5 Problems PDF

This document contains solutions to 6 questions about chapter 5 problems. It also includes VHDL code for an AND-OR logic gate entity with a behavioral architecture and a Verilog module. The code describes a process that uses a clock and reset signals to calculate the AND and OR outputs of two inputs on each positive clock edge when an enable signal is high.

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shah
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Download as PDF, TXT or read online on Scribd
38 views

Chapter 5 Problems PDF

This document contains solutions to 6 questions about chapter 5 problems. It also includes VHDL code for an AND-OR logic gate entity with a behavioral architecture and a Verilog module. The code describes a process that uses a clock and reset signals to calculate the AND and OR outputs of two inputs on each positive clock edge when an enable signal is high.

Uploaded by

shah
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Chapter 5 Problems

Question # 1:Solution:a)

b)

c)

Question # 2:Solution:-

a)

Question # 3:Solution:-

Question # 4:Solution:-

d)

Question # 5:Solution:-

Question # 6:Solution:entity AND_OR is


port (
AND_OUT : out std_logic;
OR_OUT : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
CLK : in std_logic;
CE : in std_logic;
RST : in std_logic);
end AND_OR;
architecture BEHAVIORAL_ARCHITECTURE of AND_OR is
signal and_int : std_logic;

signal or_int : std_logic;


begin
AND_OUT <= and_int;
OR_OUT <= or_int;
process (CLK)
begin
if (CLKevent and CLK=1) then
if (RST=1) then
and_int <= 0;
or_int <= 0;
elsif (CE =1) then
and_int <= I0 and I1;
or_int <= I0 or I1;
end if;
end if;
end process;
end AND_OR;
module AND_OR (AND_OUT, OR_OUT, I0, I1, CLK, CE, RST);
output reg AND_OUT, OR_OUT;
input I0, I1;
input CLK, CE, RST;
always @(posedge CLK)
if (RST) begin
AND_OUT <= 1b0;
OR_OUT <= 1b0;
end else (CE) begin
AND_OUT <= I0 and I1;
OR_OUT <= I0 or I1;
end
endmodule

Here is simulation Result:-

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