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Design and Implementation of VLSI Systems Fundamental

This document discusses the fundamentals of VLSI systems design and implementation. It covers how doping silicon affects its resistivity and the behavior of PN junctions. The document explains the operation of nMOS and pMOS transistors and how they are combined to form CMOS inverters. Additionally, it discusses various digital logic gates that can be designed using transistors, including NAND, NOR, and AOI gates. The steps for static CMOS gate design are also outlined.

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Anh Leuthar
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24 views

Design and Implementation of VLSI Systems Fundamental

This document discusses the fundamentals of VLSI systems design and implementation. It covers how doping silicon affects its resistivity and the behavior of PN junctions. The document explains the operation of nMOS and pMOS transistors and how they are combined to form CMOS inverters. Additionally, it discusses various digital logic gates that can be designed using transistors, including NAND, NOR, and AOI gates. The steps for static CMOS gate design are also outlined.

Uploaded by

Anh Leuthar
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design and Implementation of VLSI Systems

Lecture02
Fundamental

Impact of doping on silicon resistivity


silicon
4.9951022 atoms in cm3
Resistivity 3.2 105 cm
dope with
phosphorous
or arsenic
n-type

1 atom in billion 88.6 cm


1 atom in million 0.114 cm
1 atom in thousand 0.00174 cm

dope with
boron
p-type

1 atom in billion 266.14 cm


1 atom in million 0.344 cm
1 atom in thousand 0.00233 cm

Electrons are more mobile/faster than holes

What happens if we sandwich p & n types?


A

Al

p
n
B

One-dimensional
representation

In equilibrium, the drift and diffusion components of current


are balanced; therefore the net current flowing across the
junction is zero.

PN-junction regions of operation

In reverse bias, the width


of the depletion region
increases. The diode acts
as voltage-controlled
capacitor.

A forward bias
decreases the potential
drop across the
junction. As a result,
the magnitude of the
electric field decreases
and the width of the
depletion region
narrows.

nMOS and pMOS transistors


Each transistor consists of a stack of a conducting gate, an insulating
layer of silicon dioxide and a semiconductor substrate (body or bulk)
nMOS transistor
Source

Gate

pMOS transistor
Source

Drain

Gate

Drain

Polysilicon

Polysilicon

SiO2

SiO2
polysilicon
gate

n+

n+
p

bulk Si

p+

tox
n+

n+

SiO2 gate oxide


(good insulator, ox = 3.9)

p+
n

bulk Si

p-type body

Body is typically grounded

Body is typically at supply voltage

nMOS transistor
Source

Gate

Drain
Polysilicon
SiO2

n+

n+
p

g=0: When the gate is at a low voltage (VGS < VTN):


p-type body is at low voltage
source and drain-junctions diodes are OFF
transistor is OFF, no current flows
g=1: When the gate is at a high voltage (VGS VTN):
negative charge attracted to body
inverts a channel under gate to n-type
transistor ON, current flows, transistor
can be viewed as a resistor

bulk Si

nMOS pass 0 more strongly than 1


Source

Gate

Drain
Polysilicon
SiO2

n+

n+
p

Why does 1 pass degraded?

bulk Si

pMOS transistor
Source

Gate

Drain

Polysilicon
SiO2

p+

p+
n

g=0: When the gate is at a low voltage (VGS < VTP):


positive charge attracted to body
inverts a channel under gate to p-type
transistor ON, current flows
g=1: When the gate is at a high voltage (VGS VTP):
negative charge attracted to body
source and drain junctions are OFF
transistor OFF, no current flows

bulk Si

pMOS pass 1 more strongly than 0


Source

Gate

Drain

Polysilicon
SiO2

p+

p+
n

Why does 0 pass degraded?

bulk Si

An nMOS and pMOS make up an inverter

pMOS + nMOS = CMOS

More CMOS gates


B

A
B
F = AB
0

What is this gate function?

Whats wrong about this design?

3-input NANDs

If: Pull up network = 1 => pull down network must = 0


If: Pull up network = 0 => pull down network must = 1

3-input NANDs
What are the advantages of CMOS circuit style?

Series-Parallel Combinations

What are the transistor schematics of the


NOR gate?

And-Or-Inverter (AOI) gate

CMOS gate design steps


Steps:
-Design pull down network
-Use the inverse of the given function
-NMOS circuit

-Design pull up network


-Use the opposite network of the pull down network: parallel serial; serial parallel
-PMOS circuit

-Combine 2 networks

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D
Solution:
-Design pull down network Y = (A + B + C) D

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D
Solution:
-Design pull down network Y = (A + B + C) D

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D
Solution:
-Design pull down network Y = (A + B + C) D
-Design pull up network Y = (A + B + C) D

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D
Solution:
-Design pull down network Y = (A + B + C) D
-Design pull up network Y = (A + B + C) D

Examples
Example 1.2
Sketch a static CMOS gate computing Y = (A + B + C) D
Solution:
-Design pull down network Y = (A + B + C) D
-Design pull up network Y = (A + B + C) D
-Combine 2 networks:

Different design

Transmission gate

Tri-state inverter

Multiplexer (MUX)

Latch design

Flip-flop (edge triggered) design

Summary
Introduction to VLSI systems and the semiconductor industry
Basic overview of pn junctions and MOS transistors
Designing digital logic gates using transistors

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