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Counter Ps

This document contains the code for a counter module in Verilog. The counter module takes in a clock and reset signal and outputs a 8-bit counter value. It increments the counter value on each clock pulse unless the reset signal is active, in which case it resets the counter to 0. The module is intended to act as a program counter since the instruction set being modeled does not include control transfer instructions. It was written by Nestoras Tzartzanis on January 25, 1996 for an EE577b Verilog example course.

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SrinuIndia
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38 views

Counter Ps

This document contains the code for a counter module in Verilog. The counter module takes in a clock and reset signal and outputs a 8-bit counter value. It increments the counter value on each clock pulse unless the reset signal is active, in which case it resets the counter to 0. The module is intended to act as a program counter since the instruction set being modeled does not include control transfer instructions. It was written by Nestoras Tzartzanis on January 25, 1996 for an EE577b Verilog example course.

Uploaded by

SrinuIndia
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PS, PDF, TXT or read online on Scribd
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Counter Module

counter.v

96/01/24
22:50:17
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counter: The counter module.


The counter plays the role of PC since
the instruction set doesnt include any control
transfer instructions.
Parameter List:
clk:
the clock (input)
reset: it resets the counter synchronously (input)
cnt:
the output of the counter (output)
Author: Nestoras Tzartzanis
Date:
1/25/96
EE577b Verilog Example

module counter (clk, reset, cnt);


input
input
output

clk;
reset;
cnt;

[7:0]

//
reg

The outputs are defined as registers too


[7:0]
cnt;

//
The counter doesnt have any delay since the
//
output is latched when the posedge of the clock happens.
//
To be closer to the hardware implementation,
//
I could use a temporary value which would store
//
the intermediate result of the counter.
always @(posedge clk)
if (!reset)
cnt = cnt + 1;
else
cnt = 0;
endmodule

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