DDVHDL - Planning
DDVHDL - Planning
SUBJECT TITLE
SUBJECT CODE
: 9A04706
PERIODS/WEEK
:5
PERIODS/SEM
: 55
CREDITS
:4
SEMISTER SCHEDULE PLANNING
S.no
Chapter name
1
2
3
INTRODUCTION TO VERILOG
GATE LEVEL MODELLING
BEHAVIORAL MODELLING
MODELLING AT DATA FLOW
LEVEL
SYSTEM TASKS, FUNCTIONS
AND COMPILIER DIRECTIVES
DIGITAL DESIGN WITH SM
CHARTS
DESIGNING WITH
PROGRAMMABLE GATE ARRAYS
AND COMPLEX
PROGRAMMABLE LOGIC
DEVICES
VERILOG MODELS
TOTAL
4
5
Examination Schedule
I
st
II
nd
Midterm
Midterm
No. of
periods
11
6
10
Weightage
of marks
14
14
14
No. of essay
questions
1
1
1
14
14
14
14
5
52
14
80
1
1
Date
07-09-2015 to
2015
09-11-2015 to
2015
16-11-2015 to
2015
23-11-2015 to
2015
No. of days
12-0914-1121-1105-12-
6
6
6
13