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Combinational Circuit Design I: Eee 441 Logical Design Iilaboratory

This document provides the preliminary work for an experiment on combinational circuit design. It includes: 1) The objective is to design, construct, and test various combinational circuits. 2) Truth tables are given for logic functions Y=A'+B+C+D' and X=AB'C'D to be implemented using gates. 3) Additional logic functions X=AB+AC+AD+BCD and X=A' + B'C' are presented along with their truth tables to be designed with NAND and NOR gates.

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Fatih Tokgöz
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0% found this document useful (0 votes)
24 views4 pages

Combinational Circuit Design I: Eee 441 Logical Design Iilaboratory

This document provides the preliminary work for an experiment on combinational circuit design. It includes: 1) The objective is to design, construct, and test various combinational circuits. 2) Truth tables are given for logic functions Y=A'+B+C+D' and X=AB'C'D to be implemented using gates. 3) Additional logic functions X=AB+AC+AD+BCD and X=A' + B'C' are presented along with their truth tables to be designed with NAND and NOR gates.

Uploaded by

Fatih Tokgöz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EEE 441 LOGICAL DESIGN IILABORATORY

EXPERIMENT#3

COMBINATIONAL CIRCUIT DESIGN I


PRELIMINARY WORK

Mehmet BAYRAM
9610433

I. Object
In this experiment yo will design, cpnsturact and test various combinational
circuits.

II. Preliminary Work


1.
a)
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0

Y
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1

b)
Y

X
1
1
1
1

1
1
1

1
1
1
1

1
1
1
1

Y = A' + B + C + D '

X = AB 'C ' D

c)

d)

2.
%45
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

%30
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

%15
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

%10
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

X
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1

1
1

1
1
1

1
1

X = AB + AC + AD + BCD

With NAND Gates

With NOR Gates

3.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

X
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0

1
1

1
1

1
1

X = A' + B 'C '

1
1

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