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ECE342 Syllabus, Spring 2015: Brown and Vranesic Book

The ECE342 syllabus outlines 14 weeks of topics in finite state machines, digital logic, and embedded systems design. Week 1 covers finite state machines for serial adders. Weeks 2-3 focus on array multipliers and signed multiplication. Weeks 4-5 discuss array shift-and-add multipliers and algorithm implementation in hardware. Week 6 covers embedded systems design. Week 7 is reading week with no classes. Weeks 8-9 cover embedded systems and asynchronous inputs to synchronous circuits. Weeks 10-11 discuss asynchronous arbiters and state assignment. Weeks 12-13 cover state assignment and hazards in testing. Week 14 concludes with path sensitizing in testing.

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22 views

ECE342 Syllabus, Spring 2015: Brown and Vranesic Book

The ECE342 syllabus outlines 14 weeks of topics in finite state machines, digital logic, and embedded systems design. Week 1 covers finite state machines for serial adders. Weeks 2-3 focus on array multipliers and signed multiplication. Weeks 4-5 discuss array shift-and-add multipliers and algorithm implementation in hardware. Week 6 covers embedded systems design. Week 7 is reading week with no classes. Weeks 8-9 cover embedded systems and asynchronous inputs to synchronous circuits. Weeks 10-11 discuss asynchronous arbiters and state assignment. Weeks 12-13 cover state assignment and hazards in testing. Week 14 concludes with path sensitizing in testing.

Uploaded by

kinglbf
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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ECE342 Syllabus, Spring 2015

Week

Topic

Brown and
Vranesic
book

Review of Finite State Machines, FSM for


serial adder (Mealy)
8.5

Array Multiplier and Signed


Multiplication, Fast Multipliers

5.6

Array Multiplier and Signed


Multiplication, Fast Multipliers

5.6

ASM Charts, bit counting


Shift and Add multiplier

5
6
7

ASM Charts, Algorithm Implementation


in Hardware
Embedded Systems Design

8.10, 10.2.1
10.2.3
8.10, 10.2.1
10.2.3

Reading Week, No classes or labs

Embedded Systems Design, Processor


Design

Asynchronous Inputs to synchronous


circuits, Synthesis of Asynchronous FSMs 9.1, 9.2, 9.3

10

Asynchronous arbiter,
Asynchronous FSM State Minimization

9.3, 9.4

11

Merger Diagrams and State Assignment

9.4, 9.5

12

State Assignment (continued)

9.4, 9.5

13

Static Hazards,
Testing: Test sets and Path Sensitizing

9.6, 11.1,
11.2, 11.3

14

Testing: Test sets and Path Sensitizing


(cd.),

11.1-11.3

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