ANALOG ELECTRONIC CIRCUITS

LAB MANUAL
III SEMESTER B.E (E & C)
(For private circulation only)
VISHVESHWARAIAH TECHNOLOGICAL UNIVERSITY

DEPARTMENT OF ELECTRONICS & COMMUNICATION

SRI SIDDHARTHA INSTITUTE OF TECHNOLOGY

MARLUR, TUMKUR-572105

CONTENTS

Experiment No

Page. No

1. RC coupled amplifier

2. Darlington Emitter Follower

3. Voltage Series Feedback Amplifier

14

4. RC Phase shift Oscillator

22

5. Hartley & Colpitts Oscillator

26

6. Clipping circuits

30

7. Clamping circuits

40

8. Op-Amp applications

46

9. ZCD & Schmitt trigger

50

10. Full wave Precision Rectifier

54

11. Voltage Regulator

56

12. Digital-Analog Converter

60

13. Analog-Digital Converter

64

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Circuit Diagram :-

Design :-

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Experiment No:

DATE: __/__/____

RC COUPLED AMPLIFIER
AIM: -To design a RC coupled single stage FET/BJT amplifier and determination of
the gain-frequency response, input and output impedances.

APPARATUS REQUIRED:Transistor - BC 107, capacitors, resistor, power supply, CRO, function

generator, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. Set Vs = 50mV (assume) using the signal generator
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in
regular steps of 10 and note down corresponding output voltage.
4. Plot the frequency response: Gain (dB) vs Frequency (Hz).
5. Find the input and output impedance.
6. Calculate the bandwidth from the graph.
7. Note down the phase angle, bandwidth, input and output impedance.

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General Procedure for Calculation :-

1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
c. Substitute these values in the formula Z O =

Vload Vno load

100%
Vload

3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.

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Model Graph (Frequency Response) :-

TABULAR COLUMN : Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi

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Result :Theoretical
Input impedance
Output impedance
Gain (Mid band)
Bandwidth

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Practical

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Circuit Diagram :-

DC Analysis :-

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Experiment No:

DATE: __/__/____

DARLINGTON EMITTER FOLLOWER

To design a BJT Darlington Emitter follower and determine the gain, input and
AIM: -

output impedances.

APPARATUS REQUIRED:Transistor - BC 107, capacitors, resistor, power supply, CRO, function generator,
multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. Set Vi = 1 volt (say), using the signal generator
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in regular
steps of 10 and note down corresponding output voltage.
4. Plot the frequency response: Gain (dB) vs Frequency (Hz).
5. Find the input and output impedance.
6. Calculate the bandwidth from the graph.
7. Note down the phase angle, bandwidth, input and output impedance.

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Design :Given VCEQ = VCE2 = 6v

ICQ = IC2 = 5mA
Assume

for SL100 = 100

VCC = 12v

VCC 12
=
= 6v
2
2

VE2 =

IE2RE = VE2
RE =

VE2
6
=
= 1.2 k [ IE 2 = IC 2 ]
I E2 5 103

R E = 1.2k
VB1 = VBE1 + VBE 2 + VE 2
VB1 = 0.7 + 0.7 + 6
VB1 = 7.4 v
IB2 =

IC2

5 103
= 0.05mA
100

IB1 =

I C1

I B2

0.05
= 0.0005mA
100

10IB1R 1 = VCC - VB1

R1 =

R2 =

12 - 7.4
= 920k [Use R 1 = 1M]
10 0.0005 10-3

VB1
= 1644k
9I B

R 2 = 1.5M

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General Procedure for Calculation:

1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
c. Substitute these values in the formula Z O =

Vload Vno load

100%
Vload

3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.

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Model Graph: (Frequency Response)

TABULAR COLUMN: -

Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi

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4. To find Q-Point
a. Connect the circuit as per circuit diagram
b. Switch on the DC source [switch off the AC source]
c. Measure voltage at VB2, VE2 & VC2 with respect to ground
& also measure
VCE2 = VC2 - VE2
I C2 = I E2 =

V E2
RE

Q - Point = [VCE2 , I C2 ]

Result
Theoretical

Input impedance
Output impedance
Gain (Mid band)
Bandwidth

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Practical

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Circuit Diagram :Amplifier without Feedback

Amplifier with Feedback

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Experiment No:

DATE: __/__/____

VOLTAGE SERIES FEEDBACK AMPLIFIER

To design a FET/BJT Voltage series feedback amplifier and determine the
AIM: - gain, frequency response, input and output impedances with and without
feedback

APPARATUS REQUIRED:Transistor - BC 107, capacitors, resistor, power supply, CRO, function

generator, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. Set Vs = 50mV (assume) using the signal generator
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in
regular steps of 10 and note down corresponding output voltage.
4. Plot the frequency response: Gain (dB) vs Frequency (Hz).
5. Find the input and output impedance.
6. Calculate the bandwidth from the graph.
7. Note down the phase angle, bandwidth, input and output impedance.

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Design (With Feedback):Given AV1 = 30; A12 = 20; VCC = 10V; IE2 = 1.8mA; IE1 = 1.1mA; S = 3; hfe1 and hfe2
are obtained by multimeter

= 0.03

DC Analysis of II Stage: VCC = IC2RC2 + VCE2 + IE2RE2

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Model Graph (Frequency Response) :-

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General Procedure for Calculation:

1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.

2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
c. Substitute these values in the formula Z O =

Vload Vno load

100%
Vload

3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.

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TABULAR COLUMN: With Feedback (Vi = 50mV)

Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi

Without Feedback (Vi = 50mV)

Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi

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Result
Theoretical

Practical

With f/b Without f/b With f/b Without f/b

Input impedance
Output impedance
Gain (Mid band)
Bandwidth

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Circuit Diagram :-

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Experiment No:

DATE: __/__/____

RC PHASE SHIFT OSCILLATOR

AIM:
-

To design And test for the performance of RC Phase Shift Oscillator for the
given operating frequency fO.

APPARATUS REQUIRED:Transistor - BC 107, capacitors, resistor, power supply, CRO, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram (both oscillators).
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.

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Result

Theoretical Practical
Frequency

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HARTLEY OSCILLATOR:-

DESIGN:f=

1
2 LC

Assume

, where L=L1+L2

L2
= 5, Let L1=2mH L2=10mH
L1

Let Vgs =-1.5V, Id =Idss (1

gm=

Vgs 2
) = 3mA
Vp

Vgs
2 Idss
(1
) = 4mmhos
Vp
Vp

RS=

Vs Vgs 1.5
=
=
= 500
Id
Id
3m

Assume Av =10 (>

Rd =

L2
)
L1

10 =

g .Rd
m

10
= 2.5 K
4m

Assume Rg =1M , Cc1=Cc2=0.1 f,Cs=47 f,

Assuming Vds=5V
Vdd = IdRd+Vds+Vs=14V

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Experiment No:

DATE: __/__/____

HARTLEY AND COLPITTS OSCILLATOR

AIM:
-

To design and test for the performance of FET Hartley & Colpitts
Oscillators.

APPARATUS REQUIRED:Transistor BFW10, capacitors, resistor, power supply, CRO, function

generator, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram (both oscillators).
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.

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COLPITTS OSCILLATOR:-

DESIGN:f=

1
2 LC

Assume

, where C

C1C 21
C1 + C 2

C1
= 5, Let C1=500pF C2=100pF
C2

L =0.12H, for f=50KHz

Let Vgs =-1.5V, Id=Id =Idss 1

gm =

Vgs 2
) = 3mA
Vp

2 Idss Vgs
=
= 4mmhos
Vp
Vp

Rs =

Vs Vgs 1.5
=
=
= 500
Id
Id
3m

Assume Av =10 (>

Rd =

C1
)
C2

10 =

g .Rd
m

10
= 2.5 K
4m

Assume Rg =1M , Cc1=Cc2=0.1 f,Cs=47 f,

assuming Vds=5V
Vdd = IdRd+Vds+Vs=14V

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DESIGN:f = 1 MHZ =

1
2 LC

Assume L=.33H, C=0.0767pF

Let Vce = 6V, Ic = 2mA,
Choose Vcc 2 Vce
Assume Ve =

Vcc
= 1.2V
10

Re =

Ve Ve

= 1.2V
Ie
Ic

Re =

Ve Ve 1.2

=
= 600
Ie
Ic 2m

R1 =34K

Rc =

Vcc - Cce - Vre 12 6 1.2

=
= 2.4 K
Ic1
2m

Assume Cc1=Cc2=0.1 f, Ce = 47 f,

Result:Parameter

Theoretical

Frequency

Hartley

Practical
Colpitt

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Hartley

Colpitt

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Circuit Diagram:Series Clippers

a) To pass ve peak above Vr level :-

b) To pass ve peak above some level (say 3v) :-

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Experiment No:

DATE: __/__/____

CLIPPING CIRCUITS

AIM:
-

To design a Clipping circuit for the given specifications and hence to plot its
O/P

APPARATUS REQUIRED:Diode-IN 4007, capacitors, resistor, power supply, CRO, function generator,
multimeter, etc.

PROCEDURE: 1. Connections are made as shown in the circuit diagram.

2. A sine wave Input Vi whose amplitude is greater than the clipping level is
applied.
3. Output waveform Vo is observed on the CRO.
4. Clipped voltage is measured and verified with the designed values.

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c) To pass +ve peak above Vr level :-

d) To pass +ve peak above some level (say +3v) :-

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Design :Choose Rf = 10, Rr = 1M

R =

RfRr = 3.3K

a) To pass ve peak above Vr level

b) To pass ve peak above some level (say 3v)
ie.,

- (VR+Vr) = -3
VR = 3-Vr
3 0.6 = 2.4v

c) To pass +ve peak above Vr level

d) To pass +ve peak above some level (say +3v)
ie.,

(VR+Vr) = +3
VR = 3-0.6 = 2.4v

e) To pass +ve peak above some level (say +4v) and ve peak above
some level (say -3v)
ie.,

VR+Vr = 4
VR = 3.4v
-(VR+Vr) = -3v
VR = 2.4v

f) To remove +ve peak above Vr level

g) To remove +ve peak above some level (say 3v)
ie.,

(VR+Vr) = 3v
VR = 2.4v

h) To pass ve peak above some level (say -2v)

ie.,

-VR+Vr = -2
VR = 2.6v

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e) To pass +ve peak above some level (say +4v) &

-ve peak above some level (say -3v) :-

Shunt Clippers
f) To remove +ve peak above Vr level :-

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i) To remove ve peak above Vr level

j) To pass +ve peak above some level (say 2v)
ie.,

VR-Vr = 2
VR = 2.6v

k) To remove ve peak above some level (say -3v)

ie.,

-(VR+Vr) = -3
VR = 2.4v

l) To remove +ve peak above some level (say +3v) and ve peak above
some level (say -3v)
ie.,

(VR1+Vr) = 3v
VR1 = 2.4v
-(VR2+Vr) = -3v
VR2 = 2.4v

m) To pass a part of the +ve half cycle (say V1 = 2v, V2 = 4.2v)

ie.,

(VR1 - Vr) = 2v
VR1 = 2.6v
(VR2+Vr) = 4.2v
VR2 = 3.6v

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g) To remove +ve peak above some level (say +3v) :-

h) To pass ve peak above some level (say -2v) :-

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i) To remove above Vr level :-

j) To pass +ve peak above some level (say +2v) :-

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k) To remove ve peak above some level (say -3v) :-

l) To remove above some level (say +3v) and

-ve peak above some level (say -3v) :-

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m) To pass a part of the =ve half cycle (say V1 = 2v, V2 = 4.2v) :-

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Circuit Diagram:a) Positive peak clamped at Vr level :-

b) Positive peak clamped at +ve Reference :-

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Experiment No:

DATE: __/__/____
CLAMPING CIRCUITS

AIM:
-

To design a Clamping circuit for the given specifications and hence to plot
its output.

APPARATUS REQUIRED:Diode-IN 4007, capacitors, resistors, power supply, CRO, function generator,
multimeter, etc.

PROCEDURE: 1. Connections are made as shown in the circuit diagram.

2. A square wave input Vi is applied
3. Output waveform Vo is observed on the CRO. Keeping the AC/DC switch of
the CRO in DC Position.
4. Clamped voltage is measured and verified with the designed values.

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c) Positive peak clamped at ve reference level :-

d) Negative peak clamped to Vr level :-

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DESIGN :RLC >> T => Assume T = 2 ms, let RLC = 50T = 100ms
Let RL = 100K
C = 1f
a) Positive peak clamped to Vr level
b) Positive clamped to +ve reference level (say +2v)
ie., VR + Vr = 2 => VR = 2-Vr = 2 0.6 = 1.4v
c) Positive peak clamped to ve reference level (say -2v)
ie., -VR + Vr = -2 => VR = 2.6v
d) Negative peak clamped to Vr level
e) Negative peak clamped to +ve reference level (say +2v)
ie., VR Vr = 2 => VR = 2.6v
f) Negative peak clamped to ve reference level (say -2v)
ie., (VR+Vr) = -2 => VR = 1.6v

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e) Negative peak clamped at +ve reference level :-

f) Negative peak clamped at ve reference level :-

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RESULT :Circuit

Clamping level (Designed)

a)
b)
c)
d)
e)
f)

- 44 -

Clamping level (Observed)

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Circuit Diagram:INVERTING AMPLIFIER:-

NONINVERTING AMPLIFIER:-

VOLTAGE FOLLOWER:-

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Experiment No:

DATE: __/__/____

LINEAR APPLICATIONS OF OP-AMP

To design and test Operational amplifier applications: (1)Inverting
AIM:
-

Amplifier, (2) Non-Inverting Amplifier, (3) Summer, (4) Voltage Follower,

(5) Integrator and Differentiator.

APPARATUS REQUIRED:Op-Amp A 741, capacitors, resistor, Dual power supply, Regulated power
supply, CRO, function generator, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. Give the input signal as specified
3. Switch on the dual power supply.
4. Note down the outputs from the CRO.
5. Draw the necessary waveforms on the graph sheet.
6. Repeat the procedure for all circuits.
DESIGN:a) Inverting Amplifier: Let Av = 10 =
Assume Ri = 1k

Rf
Ri

Rf = 10 K , Ri = 10K

b) Non Inverting Amplifier Let Av = 11 =1 +

Assume Ri =1k

Rf
Ri

Rf = (11-1) Ri = 10k

c) Voltage follower Av =unity.

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SUMMER:-

DIFFERENTIATOR:-

INTEGRATOR:-

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DESIGN:-

a) Integrator
RC>>T
Let T=1msec and RC = 100 T = 100 msec
Assume R = 100 K

C = 1

Assume Rf = 10 K

b) Differentiator:RC<<T
Let T =1msec and Rc =0.01 f
Assume R =1K

c) Summer:Let Y=2V1+V2+3V3=
i.e,

Rf
Rf
Rf
V1 +
V2+
V3
R1
R2
R3

Rf
Rf
Rf
V3
= 2,
= 1and
R1
R2
R3

Assume Fr = 10k

R1=5K , R2=10k

Assume R = 10k

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and R3=3.33k

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Circuit Diagram:-

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Experiment No:

DATE: __/__/____

SCHMITT TRIGGER
To design and test USING Operational amplifiers for the performance of:
AIM:
-

(1)Zero

Crossing Detector, (2) Schmitt Trigger for different hysterisis

values.

APPARATUS REQUIRED:Op-Amp A 741, capacitors, resistor, Dual power supply, Regulated power
supply, CRO, function generator, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. For a zero crossing detector, connect the non-inverting terminal to ground.
3. Switch on the dual power supply.
4. Observe the output waveform on the CRO
5. Draw the output and input waveforms.
6. For Schmitt Trigger set input signal (say 1V, 1 KHz) using signal generator.
7. Observe the input and output waveforms on the CRO.
8. Plot the graphs: Vi vs Time, VO vs Time.

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WAVE FORMS:-

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DESIGN:VRRI
VsatR 2
+
R1 + R 2 R1 + R 2

Let UTP = 6V =

VRRI
VsatR 2
+
R1 + R 2 R1 + R 2

LTP = - 2V =

Assume Vsat = 12V

2VRRI
R1 + R 2

VR =

2( R1 + R 2)
R2
= 2(1 +
)
R1
R1

2VsatR 2
R1 + R 2

VR =

R1
=2
R2

UTP + LTP =4 =

UTP - LTP =8 =

VR = 3V, Assume R2 = 1 K

R1 = 2 K

IIIIy design for UTP = + 4, +8, +2 and -2.

LTP = - 4, + 2, - 4 and = 4

RESULT: -UTP and LTP is measured and compared with the designed value.

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FULL WAVE PRECISION RECTIFIER:-

DESIGN:-

(i) Given A =

5
Rf
= 10 =
0.5
Ri

Assume Ri = 1k , Rf = 10K
Choose R = 10K
Rf' = Rf = 10K
(ii) Given A1 =

3
Rf
Rf '
5
Rf
= 10 =
=6=3
and A2 =
0.5
Ri 2R + Rf '
0.5
Ri

Assume Ri = 1K
Rf = 10K and Rf' = 5K

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Experiment No:

DATE: __/__/____

FULL WAVE PRECISION RECTIFIER

AIM:
-

To test for the performance of Full wave Precision Rectifier using

Operational Amplifier.

APPARATUS REQUIRED:Op-Amp A 741, capacitors, resistor, Dual power supply, Regulated power
supply, CRO, function generator, multimeter, etc.
PROCEDURE: 1. Connect the circuit as per the circuit diagram.
2. Give a sinusoidal input of VPP, 1 KHz from a signal generator.
3. Switch on the power supply and note down the output from CRO.
4. Without Connecting Rf 2, the wave form of the half wave rectifier is produced.
5. At some value of Rf 2 the wave form of a full wave rectifier is obtained.
6. Repeat the above procedure by reversing the diodes.

RESULT:The operation of the precision rectifier is studied using A 741.

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CIRCUIT DIAGRAM: - (HIGH VOLTAGE)

DESIGN:Given VO = 12 v
VO = 7.15 1 +
12 = 7.15 1 +

R1
R2

R1
R2

Assume R 1 = 10K

R 2 = 17.7K [use 15K ]

Assume R L = 720 & C = 100pf

CHARACTERISTIC CURVE: -

OBSERVATION:Vi (volts)

Vo
(volts)

7v

Vi (volts)

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Vo (volts)

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Experiment No:

DATE: __/__/____

VOLTAGE REGULATOR USING IC 723

AIM: -

To design and test the IC 723 voltage regulator.

APPARATUS REQUIRED:IC 723, capacitors, resistor, power supply, CRO, function generator,
multimeter, etc.
PROCEDURE: 1. Connect the circuit as per the circuit diagram.
2. Switch on the power supply and note down the output from CRO.
3. Vary the input voltage from 7V, note down corresponding output voltage.
4. Draw the regulation charectistics.

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Analog Electronic Circuits Lab

SSIT

CIRCUIT DIAGRAM: - (LOW VOLTAGE)

DESIGN:-

For LM723 Vref = 7.15V

VO = 7.15

R2
R1 + 2

Let the devider current I O through the resistor R 1 & R 2 is 1mA. Since error
amplifier draws very little current, we will neglect its input bias current.
Hence R 1 =

Vref VO 7.15 6
= 1.1K
=
ID
1 10 3

R2 =

VO
6
= 6K
=
I D 1 10 3

R3 =

R 1R 2
= _________
R1 + R 2

Assume C1 = 0.1F & C 2 = 100PF

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Analog Electronic Circuits Lab

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PROCEDURE:1. Connect the circuit as per the circuit diagram.

2. For line regulation vary the input voltage from 7V, note down the
corresponding output voltage.
3. Draw the transfer characteristics.
4. For load regulation note down the output current.
5. Draw the transfer characteristics.
GRAPH:(i) Line Regulation

(ii) Load Regulation

Vo
(volts)

Vo
(volts)

Vi (volts)

Io (mA)

OBSERVATION:(i) Line Regulation

(ii) Load Regulation

Vi (volts) Vo (volts)

Vi (volts)

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Vo (volts)

Analog Electronic Circuits Lab

SSIT

CIRCUIT DIAGRAM: -

V0 = R f

b 3 b 2 b1
b
+
+
+ 0 Vref
2R 4R 8R 16R

Note: 1. b3, b2, b1 and b0 are binary input.

2. Vref = 5V.
3. If b is the decimal value of the binary input b3, b2, b1, b0, then V0 =

Vref
b
8

4. Vo is the analog output

5. Binary inputs can either take the value 0 or 1
6. Binary input bi can be made 0 by connecting the input to the ground. It can be
made 1 by connecting to +5V

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Analog Electronic Circuits Lab

SSIT

Experiment No:

DATE: __/__/____

VOLTAGE REGULATOR USING IC 723

AIM: -

To design 4 bit R-2R ladder DAC using op-amp.

APPARATUS REQUIRED:IC 723, resistor, power supply, CRO, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.
2. The IC is given proper bias of +12V and -12V to Vcc and Vee
respectively.
3. According to the binary values of b3, b2, b1 and b0, b3, b2, b1 and b0 are
connected to +5V or Ground respectively.
4. The o/p voltage is tabulated for different binary inputs and is compared with
the theoretical values.

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Analog Electronic Circuits Lab

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O/P vs I/P

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Analog Electronic Circuits Lab

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Tabular Column:Inputs

Output (volts)

b3 b2, b1 b0 Practical Theoretical

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Analog Electronic Circuits Lab

SSIT

CIRCUIT DIAGRAM: - (2 BIT Flash type ADC)

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Analog Electronic Circuits Lab

SSIT

Experiment No:

DATE: __/__/____
ANALOG TO DIGITAL CONVERTOR

AIM: - To rig up circuit to convert an analog voltage to its digital equivalent

APPARATUS REQUIRED:IC LM 324, IC 7400, resistor, power supply, multimeter, etc.

PROCEDURE: 1. Connect the circuit as per the circuit diagram.

2. Verify the digital O/P for different analog voltages.

Note:- (1). Connect V+ (pin 4) terminal of the OPAMP to +5V

(2). Connect V- (pin 11) terminal of the OPAMP to ground

Design: Number of comparators required = 2n-1

Where n = desired number of bits
C1, C2 & C3 = Comparator o/p
D0 & D1 = Encoder (Coding network) O/P

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Analog Electronic Circuits Lab

SSIT

PIN DIAGRAM:-

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Analog Electronic Circuits Lab

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Tabular Column:-

Analog I/P Vin C3 C2 C1 D1 D0

0 to v/4

V/4 to V/2

V/2 to 3V/4

3V/4 to V

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