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ARM Cortex-M0+ Instruction Set ARM Cortex-M0+ Instruction Set

The document describes the instruction set architecture of the ARM Cortex-M0+ processor. It lists the various instruction mnemonics along with their register transfer notation descriptions. The instructions cover data movement, arithmetic, logic, shift, memory access, conditional and unconditional branching, and miscellaneous functions. The instruction set is designed for small embedded applications with a focus on efficiency and simplicity.

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Ngoc Vinh Huynh
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
501 views

ARM Cortex-M0+ Instruction Set ARM Cortex-M0+ Instruction Set

The document describes the instruction set architecture of the ARM Cortex-M0+ processor. It lists the various instruction mnemonics along with their register transfer notation descriptions. The instructions cover data movement, arithmetic, logic, shift, memory access, conditional and unconditional branching, and miscellaneous functions. The instruction set is designed for small embedded applications with a focus on efficiency and simplicity.

Uploaded by

Ngoc Vinh Huynh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ARM Cortex-M0+ Instruction Set

Mnemonic

Operation
Data Movement
MOV Rx,Ry
Move
MOVS Ra,Rb
Move; set (N, Z)
MOVS Ra,#Imm8 Move; set (N, Z)
MRS Rj,RSpecial Move to register from special
MSR RSpecial,Rj Move to special from register;
set (N, Z, C, V)
MVNS Ra,Rb
Move not; set (N, Z)
REV Ra,Rb
Reverse byte order
REV16 Ra,Rb
Reverse byte order of halfwords
REVSH Ra,Rb
SXTB Ra,Rb
SXTH Ra,Rb

Reverse signed halfwords


Sign-extend byte
Sign-extend halfword

UXTB Ra,Rb
UXTH Ra,Rb

Unsigned extend byte


Unsigned extend halfword

Register Transfer Notation


Rx Ry
Ra Rb
Ra ZeroExt(Imm8)
Rj RSpecial
RSpecial Rj
Ra ~Rb
Ra Reverse byte order (Rb)
Ra Reverse byte order
of halfwords (Rb)
Ra Reverse halfwords (Rb)
Ra SignExtend (Byte(Rb))
Ra SignExtend
(Halfword(Rb))
Ra ZeroExtend (Byte(Rb))
Ra ZeroExtend
(Halfword(Rb))

Imm3 [0, 7], unsigned 3-bit number


Imm5 [0, 31], unsigned 5-bit number
Imm5+ [1, 32], counting 5-bit number
Imm62 [0, 62], unsigned 6-bit number that is a multiple of 2
Imm74 [0, 124], unsigned 7-bit number that is a multiple of 4
Imm8 [0, 255], unsigned 8-bit number
ImmS82 [-256, 254], signed 8-bit number that is a multiple of 2
Imm94 [0, 508], unsigned 9-bit number that is a multiple of 4
Imm104 [0, 1020], unsigned 10-bit number that is a multiple of 4
ImmS25 [-224, 224 - 1], unsigned 25-bit number that is a multiple of 4
Ra, Rb, Rc: R0 through R7
Rj: LR or R0 through R12
RLoList: One or more registers from R0 through R7
Rm, Rn: R0 through R14
RPopList: One or more registers from PC and R0 through R7
RPushList: One or more registers from LR and R0 through R7
Rt: SP or PC
Rx, Ry, Rz: R0 through R15

R. W. Melton 2/9/2015

ARM Cortex-M0+ Instruction Set

Mnemonic

Operation
Register Transfer Notation
Arithmetic
ADCS Ra,Ra,Rb
Add with carry; set (N, Z, C, V)
Ra Ra + Rb + C
ADD Rx,Rx,Ry
Add
Rx Rx + Ry
ADD Rx,Rt,#Imm104 Add
Rx Rt + ZeroExt(Imm104)
ADD SP,SP,#Imm94
Add
SP SP + ZeroExt(Imm94)
ADDS Ra,Rb,Rc
Add; set (N, Z, C, V)
Ra Rb + Rc
ADDS Ra,Ra,#Imm8 Add; set (N, Z, C, V)
Ra Ra + ZeroExt(Imm8)
ADDS Ra,Rb,#Imm3 Add; set (N, Z, C, V)
Ra Rb + ZeroExt(Imm3)
CMN Ra,Rb
Compare negative; set (N, Z, C, V) Ra + Rb
CMP Rm,Rn
Compare; set (N, Z, C, V)
Rm - Rn
CMP Rm,#Imm8
Compare; set (N, Z, C, V)
Rm - ZeroExt(Imm8)
MULS Ra,Rb,Ra
Multiply; set (N, Z)
Ra Rb Ra
NOP
No operation
RSBS Ra,Rb,#0
Reverse subtract; set (N, Z, C, V)
Ra 0 - Rb
SBCS Ra,Ra,Rb
Subtract with carry;
Ra Ra - Rb - C
set (N, Z, C, V)
SUB SP,SP,#Imm94
Subtract
SP SP - ZeroExt(Imm94)
SUBS Ra,Rb,Rc
Subtract; set (N, Z, C, V)
Ra Rb - Rc
SUBS Ra,Ra,#Imm8
Subtract; set (N, Z, C, V)
Ra Ra - ZeroExt(Imm8)
SUBS Ra,Rb,#Imm3
Subtract; set (N, Z, C, V)
Ra Rb - ZeroExt(Imm3)
Logic
ANDS Ra,Ra,Rb
And; set (N, Z)
Ra Ra & Rb
BICS Ra,Ra,Rb
Bit clear; set (N, Z)
Ra Ra & ~Rb
EORS Ra,Ra,Rb
Exclusive or; set (N, Z)
Ra Ra Rb
ORRS Ra,Ra,Rb
Or; set (N, Z)
Ra Ra | Rb
TST Ra,Rb
Test bits; set (N, Z)
Ra & Rb
Shift
ASRS Ra,Ra,Rb
Arithmetic shift right; set (N, Z, C) Ra Ra >> Rb (arithmetic)
ASRS Ra,Rb,#Imm5+ Arithmetic shift right; set (N, Z, C) Ra Rb >> Imm5+ (arithmetic)
LSLS Ra,Ra,Rb
Logical shift left; set (N, Z, C)
Ra Ra << Rb (logical)
LSLS Ra,Rb,#Imm5
Logical shift left; set (N, Z, C)
Ra Rb << Imm5 (logical)
LSRS Ra,Ra,Rb
Logical shift right; set (N, Z, C)
Ra Ra >> Rb (logical)
LSRS Ra,Rb,#Imm5+ Logical shift right; set (N, Z, C)
Ra Rb >> Imm5+ (logical)
RORS Ra,Ra,Rb
Rotate right; set (N, Z, C)
Ra Ra >> Rb (circular)
Imm3 [0, 7], unsigned 3-bit number
Imm5 [0, 31], unsigned 5-bit number
Imm5+ [1, 32], counting 5-bit number
Imm8 [0,255], unsigned 8-bit number
Imm94 [0, 508], unsigned 9-bit number that is a multiple of 4
Imm104 [0, 1020], unsigned 10-bit number that is a multiple of 4

R. W. Melton 2/9/2015

ARM Cortex-M0+ Instruction Set

Memory
ADR Ra,[PC,#Imm104] Load address
ADR Ra,Label
LDM Ra!,{RLoList}
Load multiple
with Ra not in {RLoList}:
N = |{RLoList}|; i[0, N-1]
LDM Ra,{RLoList}
Load multiple
with Ra in {RLoList}:
N = |{RLoList}|; i[0, N-1]
LDR Ra,[PC,#Imm104] Load address
LDR Ra,Label
LDR Ra,[Rb,Rc]
Load register
LDR Ra,[Rb,#Imm74]
Load register
LDR Ra,[SP,#Imm104] Load register
LDRB Ra,[Rb,Rc]
Load register byte
LDRB Ra,[Rb,#Imm5] Load register byte
LDRH Ra,[Rb,Rc]
Load register halfword
LDRH Ra,[Rb,#Imm62] Load register halfword
LDRSB Ra,[Rb,Rc]
Load register signed byte
LDRSH Ra,[Rb,Rc]
Load register signed halfword
POP {RPopList}
Pop registers from stack:
N = |{RPopList}|; i[0, N-1]

Ra PC + ZeroExt(Imm104)
Imm104 = PC - Label
Rbi M[Ra + 4i]
" Rbi {RLoList}
Ra Ra + 4N
Rbi M[Ra + 4i]
" Rbi {RLoList}

Ra M[PC + ZeroExt(Imm104)]
Imm104 = PC - Label
Ra M[Rb + Rc]
Ra M[Rb + ZeroExt(Imm74)]
Ra M[SP + ZeroExt(Imm104)]
Ra M[Rb + Rc]
Ra M[Rb + ZeroExt(Imm5)]
Ra M[Rb + Rc]
Ra M[Rb + Zeroext(Imm62)]
Ra M[Rb + Rc]
Ra M[Rb + Rc]
Rxi M[SP + 4i]
" Rxi {RPopList}
SP SP + 4N
PUSH {RPushList}
Push registers on stack:
Rxi M[SP - 4(N-i)]
N = |{RPushList}|; i[0, N-1]
" Rxi {RPushList}
SP SP - 4N
STM Ra!,{RLoList}
Store multiple;
M[Ra + 4i] Rbi
if Ra in {RLoList}, must be first:
" Rbi {RLoList}
N = |{RLoList}|; i[0, N-1]
Ra Ra + 4N
STR Ra,[Rb,Rc]
Store register
M[Rb + Rc] Ra
STR Ra,[Rb,#Imm74]
Store register
M[Rb + ZeroExt(Imm74)] Ra
STR Ra,[SP,#Imm104] Store register
M[SP + ZeroExt(Imm104)] Ra
STRB Ra,[Rb,Rc]
Store register byte
M[Rb + Rc] Ra
STRB Ra,[Rb,#Imm5]
Store register byte
M[Rb + ZeroExt(Imm5)] Ra
STRH Ra,[Rb,Rc]
Store register halfword
M[Rb + Rc] Ra
STRH Ra,[Rb,#Imm62] Store register halfword
M[Rb + ZeroExt(Imm62)] Ra
Imm5 [0, 31], unsigned 5-bit number
Imm62 [0, 62], unsigned 6-bit number that is a multiple of 2
Imm74 [0, 124], unsigned 7-bit number that is a multiple of 4
Imm104 [0, 1020], unsigned 10-bit number that is a multiple of 4
Ra, Rb, Rc: R0 through R7

R. W. Melton 2/9/2015

ARM Cortex-M0+ Instruction Set

Conditional Branch to Label within 256 bytes encoded as ImmS82


Branch carry clear
CC: PC Label
Branch carry set
CS: PC Label
Branch equal
EQ: PC Label
Branch greater than or equal
GE: PC Label
Branch greater than
GT: PC Label
Branch higher
HI: PC Label
Branch higher or same
HS: PC Label
Branch less than or equal
LE: PC Label
Branch lower
LO: PC Label
Branch lower or same
LS: PC Label
Branch less than
LT: PC Label
Branch minus
MI: PC Label
Branch not equal
NE: PC Label
Branch plus
PL: PC Label
Branch overflow clear
VC: PC Label
Branch overflow set
VS: PC Label
Unconditional Branch
B Label
Branch to Label
PC Label
BAL Label
(Label within 2 KB)
BL Label
Branch with link to Label
LR PC - 2
(Label within 16 MB)
PC Label
BLX Rj
Branch exchange with link
LR PC - 2
PC Rj
BX Rj
Branch exchange
PC Rj
Miscellaneous
BKPT #Imm8 Breakpoint
Enter debug state
CPSID I
Mask interrupts
PRIMASK.PM 1
CPSIE I
Unmask interrupts
PRIMASK.PM 0
DMB
Data memory barrier
Complete previous memory accesses
before next memory access
DSB
Data synchronization barrier
Complete previous memory accesses
ISB
Instruction synchronization barrier Complete previous instructions
SEV
Send event
Signal all processors;
set local event register
SVC #Imm8
Supervisor call
Cause SVC exception
WFE
Wait for event
Wait for event
WFI
Wait for interrupt
Wait for interrupt
Imm8 [0, 255], unsigned 8-bit number
ImmS82 = ((PC - Label) 2) [-256, 254], signed 8-bit number that is a multiple of 2
Rj: LR or R0 through R12
BCC Label
BCS Label
BEQ Label
BGE Label
BGT Label
BHI Label
BHS Label
BLE Label
BLO Label
BLS Label
BLT Label
BMI Label
BNE Label
BPL Label
BVC Label
BVS Label

R. W. Melton 2/9/2015

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