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Lecture3 MOS Transistor

The document describes the MOS transistor, which is the basic building block of digital integrated circuits. It discusses the structure of an NMOS transistor including the gate, source, drain and substrate. It also describes the switch model and how applying a voltage to the gate can open or close the channel between source and drain. Additionally, it covers the static and dynamic behavior of MOS transistors such as the different regions of operation including linear, saturation and cutoff based on voltages applied.

Uploaded by

Kartika Munir
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
273 views

Lecture3 MOS Transistor

The document describes the MOS transistor, which is the basic building block of digital integrated circuits. It discusses the structure of an NMOS transistor including the gate, source, drain and substrate. It also describes the switch model and how applying a voltage to the gate can open or close the channel between source and drain. Additionally, it covers the static and dynamic behavior of MOS transistors such as the different regions of operation including linear, saturation and cutoff based on voltages applied.

Uploaded by

Kartika Munir
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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The Devices:

MOS Transistor

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]


EE415 VLSI Design

The MOS Transistor


Polysilicon Aluminum

EE415 VLSI Design

The MOS Transistor


Gate Oxyde
Gate
Source

Polysilicon

n+

Drain
n+

p-substrate

Bulk Contact

CROSS-SECTION of NMOS Transistor

EE415 VLSI Design

Field-Oxyde
(SiO2)

p+ stopper

Switch Model of NMOS


Transistor
| VGS |

Source
(of carriers)

Open (off) (Gate = 0)

Gate
Drain
(of
carriers)
Closed (on) (Gate = 1)
Ron

| VGS | < | VT |

EE415 VLSI Design

| VGS | > | VT |

Switch Model of PMOS


Transistor
| VGS |

Source
(of carriers)

Open (off) (Gate = 1)

Gate
Drain
(of carriers)

Closed (on) (Gate = 0)


Ron

| VGS | > | VDD | VT | |


EE415 VLSI Design

| VGS | < | VDD |VT| |

MOS transistors Symbols


D

G
S

NMOS Enhancement NMOS Depletion


D

G
S

PMOS Enhancement

EE415 VLSI Design

B
S

NMOS with
Bulk Contact

Channe
l

MOSFET Static Behavior


Positive voltage applied to the gate (VGS > 0)
The gate and substrate form the plates of a capacitor.
Negative charges accumulate on the substrate side (repels
mobile holes)
A depletion region is formed under the gate (like pn junction
+
diode)
S
D
VGS
-

n+

n+

n-channel

Depletion
Region
p-substrate

EE415 VLSI Design

Current-Voltage Relations
Assume VGS > VT

A voltage difference VDS will cause ID to flow from drain to source


At a point x along the channel, the voltage is V(x), and the gate-tochannel voltage is VGS - V(x)
For channel to be present from drain to source, VGS - V(x) > VT,
i.e. VGS - VDS > VT forS channel
toV exist from drain to source
V
GS

DS

G
n+

V(x)

ID

D
n+

+
L

p-substrate
B

EE415 VLSI Design


MOS transistor and its bias conditions

Linear (triode) Region


When VGS - VDS > VT , the channel exists from drain to
source
Transistor behaves like voltage controlled resistor

EE415 VLSI Design

Saturation Region
When VGS - VDS VT , the channel is pinched of
Electrons are injected into depletion region and
accelerated towards drain by electric field
Transistor behaves like voltage-controlled current
source

EE415 VLSI Design

Pinch-of

Current-Voltage Relations
Long-Channel Device

EE415 VLSI Design

Current-Voltage Relations
Long Channel transistor
6

x 10

-4

VGS= 2.5 V

VDS = VGS - VT

Resistive

4
ID (A)

VGS= 2.0 V

VGS= 1.5 V

Quadratic
Relationship

VDS = VGS - VT

cut-off

Saturation

VGS= 1.0 V
0

0.5

VDS (V)

1.5

2.5

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V


EE415 VLSI Design

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