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Assignment #1 For The Course: VLSI-Architecture Semester: Spring 2015 Course Instructor: Dr. Rahul Shrestha

This document outlines the 3 assignments for a VLSI architecture course in spring 2015 taught by Dr. Rahul Shrestha. The first assignment asks to represent 4-bit carry look-ahead and ripple adders at different levels of abstraction from structural perspective. The second assignment asks to list differences between backend VLSI, FPGA/CPLD, and microprocessor design and provide examples. The third assignment involves behavioral simulation, deriving a data dependency graph and isomorphic architecture, writing HDL code, synthesis, and test bench simulation for a 16-input comparator to find maximum and minimum values.

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Sai Vishnu R
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87 views

Assignment #1 For The Course: VLSI-Architecture Semester: Spring 2015 Course Instructor: Dr. Rahul Shrestha

This document outlines the 3 assignments for a VLSI architecture course in spring 2015 taught by Dr. Rahul Shrestha. The first assignment asks to represent 4-bit carry look-ahead and ripple adders at different levels of abstraction from structural perspective. The second assignment asks to list differences between backend VLSI, FPGA/CPLD, and microprocessor design and provide examples. The third assignment involves behavioral simulation, deriving a data dependency graph and isomorphic architecture, writing HDL code, synthesis, and test bench simulation for a 16-input comparator to find maximum and minimum values.

Uploaded by

Sai Vishnu R
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment #1 for the course: VLSI-Architecture

Semester: Spring 2015


Course Instructor: Dr. Rahul Shrestha
-----------------------------------------------------------------------------------------------------------------------------------------------------------1.

Represent 4-bit carry look-ahead and ripple adders into various levels of abstraction from structural perspective.
These levels of abstraction are as follows:
Top blocks and I/Os.
Sub-blocks.
ALUs, registers and memories.
Gates latches and flip-flops.
Transistors and wires.

2.

List out major differences between back-end VLSI design, back-end FPGA/CPLD design and back-end
microprocessor design. Give example for each of these designs.

3.

A comparator shown in figure below has 16 inputs with 8-bit quantization and there are two outputs: maximum
and minimum values of these 16 inputs. For such design:
Carryout behavioral simulation using any of the high-level languages like MATLAB or C or
C++ etc. (Code must be enclosed).
Derive data dependency graph (DDG) and isomorphic architecture for this comparator.
Write hardware description for this architecture using any of the HDLs like Verilog or VHDL
or System Verilog etc. (Code must be enclosed).
Synthesize the code in ISE design environment to generate the timing and hardware
consumption reports (Synthesis report must be enclosed).
Write a test-bench for this architecture and test its functionality by simulating in ISE
environment. (Input and output Waveform must be enclosed).

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