Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4-1

Chapter 4. Circuit Characterization and Performance Estimation

4.1 introduction.

Each layer of transistor-forming material has both a resistance and a capacitance that are fundamental
components in estimating the performance of a circuit or a system. (It also has inductance but insignificant
for most on-chip circuit.)

The issues considered in this chapter are

Resistance , capacitance, and inductance calculations.

Delay estimations
Determination of conductor size for power and clock distribution.
Power consumption
Charge sharing mechanism
Design margining
Reliability
Effects of scaling

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.2 Resistance Estimation

l
l
The resistance of a uniform conducting slab is R = = R s
w
t w
where = resistivity.
t = thickness.
l = conductor length.
w = conductor width.
Rs = Sheet resistance having units of /square.

According to the above formula, the two metal slabs shown in Figure 4.1 have the same resistance.

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Chapter 4:Circuit Characterization and Performance Estimation

Table 4.1 shows typical sheet resistances for 0.54m to 1.04m MOS process

Note that for metal having a given thickness, the resistivity is known, while for ploy and diffusion the
resistivities are significantly influenced by the concentration density of the imparities.

From the voltage-current characteristic of an MOS transistor, the channel resistance in the linear region
can be approximated as Rc = k (

L
1
) , where k =
W
C ox(Vgs Vt )

derived from equation (2.14), 1000

< k < 30000 /square for n- and p-channel devices.

Since the mobility of the majority carriers decreases with the increase of temperature, the channel
resistance is increased by approximately 0.25% per oC for temperature above 25 oC.

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Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.21 Resistance of Nonrectangular Regions

Figure 4.2(a) summarizes the resistance of a number of commonly encountered shapes.

Figure 4.2(b) shows some shapes that are commonly encountered in practice.

Table 4.2 represents the results of a study to calculate the resistance of the shapes shown in Figure 4.2(b)
for different dimension ratio.

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Chapter 4:Circuit Characterization and Performance Estimation

4.2.2 Contact and Via Resistance

Rung-Bin Lin

Typical values for processes currently in use (0.6m) range form 0.25 to a few tens of s.

4.3 Capacitance Estimation

The total load capacitance on the output of a CMOS gate is the sum of
gate capacitance ( of other inputs connected to the output of the logic gate )
diffusion capactance ( of the drain regions connected to the output)
routing capacitance ( of connections between the output and other inputs )

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Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.3.1 MOS - Capacitor Characteristics

The capacitance-voltage characteristics of an MOS capacitor ( i.e. an MOS transistor without source or
drain ) depend on the state of the semiconductor surface.

The surface for a p-substrate structure shown in Figure 4.3 may be

accumulation when Vg < 0 (see Figure 4.3 (a)), and the gate capacitance may be approximaterd by
sio o
C0 = 2 A
, where
t ox
A = area of gate.
SiO2 = dielectric constant (or relative permittivity of SiO2, taken as 3.9)
o = permittivity of free space.
depletion when Vg > 0 ( See Figure 4.3 (b)), and the gate capacitance
C0 C dep

C gb =
< Co , where C dep = ( o Si )A is the depletion capacitance, decreased when d
C0 + Cdep
d
increases.
d = depletion layer depth, increased when gate to substrate voltage increases.

Si = dielectric constant of silicon, taken as 12.

inversion as Vg is further increased ( see Figure 4.3 (c)). In this case, minority carries ( electrons for
the p-substrate ) are attracted forward the silicon surface and thus created an n-channel. Surface
inversion yields a relative high conductivity layer under the gate. Thus for low frequency operation
( < 100Hz), Cgb=Co; For high frequency operation, the surface change is not able to track fast
moving gate voltages
Co Cdep
C gb =
< Co
C0 + Cdep

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Chapter 4:Circuit Characterization and Performance Estimation

As it can be seen, if Vg increases, the total capacitance decreases.

Figure 4.3 (a) plots the dynamic gate capacitance as a function of gate voltage.

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Chapter 4:Circuit Characterization and Performance Estimation

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4-8

4.3.2 MOS Device capacitances.

Figure 4.4 is a diagramatic representation of the parasistic capacitance fo an MOS transistor. It is assumed
that the overlap of the gate over source/drain is equal to zero.

The following capacitance components exist:

Cgs, Cgd = gate to channel capacitances, lumped at the source and the drain regions of the channel,
respectively.
Csb, Cdb = source and drain-diffusion capacitance to bulk (or substrate).
Cgb = gate to bulk capacitance.

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

Figure 4.5 shows a circuit model comprising parasitic copacitances and the transistor. The total gate
capacitance is given by Cg = Cgb + Cgs + Cgd.

The behavior of gate capacitance of an MOS device:

1. Off region, where Vgs < Vt, no channel exists, hence Cgs = Cgd =0. So Cg = Cgb.
2. Non-saturated region, where Vgs - Vt > Vds. A channel exists. Thus
1 0 SiO 2
C gd = C gs =
A and Cgb = 0.
2 t ox
3. Saturated region, where Vgs - Vt < Vds. The channel is pinched off at the drain end. Thus
Cgd =0 and

C gs =

2 0 SiO 2
A .
3 t ox

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The behavior of the gate capacitance is shown in Table 4.3 where = O SiO2

Figure 4.6 (a) shows the Cgs and Cgd of a long channel n-transistor (W = 49.2 m, L=4.5 m).

Figure 4.6 (b) shows the Cgs and Cgd of a short channel device (L=0.75 m). Note that Cgd is finite, i.e., Cgd
> 0. This is due to channel side fringing fields between the gate and drain.

Chapter 4:Circuit Characterization and Performance Estimation

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Rung-Bin Lin

Chapter 4:Circuit Characterization and Performance Estimation

For the purpose of delay calculation, the gate capacitance can be approximated by
C g = Cox A =

o SiO 2

A, where Cox = o SiO 2
t ox
t ox

is the thin-oxide capacitance per unit area.

3.9*8.854*10 14
With a thin-oxide thickness ( tox ) in the order of 100 200, Cox =
( 100 200 )*10 8
= 35 17*10-4 pF/ m2.

The gate capacitance for the case shown in Figure 4.7 for = 0.5 m, W = 2 m and L = 1 m and
tox=150 , is Cg(intrinsic) = 2*25.5*10-4pF = 0.005 pF.

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Chapter 4:Circuit Characterization and Performance Estimation

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4.3.3 Diffusion (source/drain) capacitance.

Figure 4.8 shows a model for source/drain capacitance. Total drain capacitance Cd is given by
Cd=Cja*(ab)+Cjp*(2a+2b),

where Cja = junction capacitance per m2,

Cjp = periphery capacitance per m.
a = width of diffusion region ( m).
b = length of diffusion region ( m).

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Chapter 4:Circuit Characterization and Performance Estimation

Table 4.4 shows typical values of diffusion capacitances for both n- and p-channel devices.

Note that the above simple capacitance calculations assume zero DC bias across the junction. However,

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both Cja and Cjb are functions of junction voltage Vj due to dependence of depletion layer thickness on Vj.
Thus the junction capacitance is

C j = C jo (1

Vj
Vb

) m

where Vj = junction voltage (negative for reversed-bias)

Cjo = zero bias capacitance (i.e., Vj=0)
Vb = built-in junction potential ~ 0.6 volts.
m = a constant dependent on the distribution of impurities. Effective value ranges from 0.3 ~ 0.5.

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.3.4 SPICE Modeling of MOS capacitance

The SPICE MOSFET ( and the corresponding model ) call and the MOSFET MODEL statement are
shown below

AS = source area,
AD = drain area,
PS = source periphery,
PD = drain periphery.
.MODEL signals the beginning of MOSFET model

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From these data, Cg(intrinsic) = W * L * Cox = 4*1*17*10-4 pF = 0.0068pF. Cox is derived form TOX =
200E-8.

Extrinsic values of Cgso, Cgdo and Cgbo are added to Cgs, Cgd and Cgb to consider the fringing field from gate
terminal . They are specified in SPICE MOSFET Model by CGSO, CGDO and CGBO.

Cgbo occurs due to the polysilcon ( gate ) extension beyond the channel. Thus Cgbo = CGSO * L * 2.

Cgso and Cgdo represent the gate source/drain capacitance due to overlap in the physical structure of the
transistor. Thus, Cgso = CGSO * W and Cgdo = CGDO * W.

The extrinsic gate capacitance for a typical MOS transistor is

Cg(extrinsic) = Cgso + Cgdo + Cgbo = W*CGSO + W*CGDO + 2 * L * CGBO.
= 4*600*10-12*10-6+4*600*10-12*10-6+2*1*200*10-12*10-6 = 0.0052pF.

Cg(total) = Cg(intrinsic) + Cg(extrinsic) = 0.0068 + 0.0052 =0.012pF.

Chapter 4:Circuit Characterization and Performance Estimation

In SPICE the source/drain capacitance is calculated as follows:

C j = ( Area * CJ * (1 +

VJ MJSW
VJ MJ
)
+ ( Periphery * CJSW ) * (1 +
)
)
PB
PB

where CJ = the zero-bias capacitance per junction area.

CJSW = the zero-bias-junction capacitance per junction periphery.
MJ = the grading coefficient of the junction bottom.
MJSW = the grading coefficient of the junction sidewall.
VJ = the junction potential.
PB = the built-in voltage (0.4 0.8V)
Area = AS or AD, the area of source/drain
Periphery = PS or PD, the periphery of source/drain.

At VJ = 2.5V and PB = 0.7V,

Cj drain = [15*10-12*2*10-4*(1+2.5/0.7)-0.5]+[11.5*10--6*4*10--10*(1+2.5/0.7)-0.3]F
= 0.0014pF +0.0029pF = 0.0043pF = Cj source

Rung-Bin Lin

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Chapter 4:Circuit Characterization and Performance Estimation

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4.3.5 Routing Capacitance

4.3.5.1 Single Wire Capacitance

Routing capacitance between metal and poly layers and the substrate is shown in Figure 4.9. It consists of
three components:
1. A parallel-plate capacitance ( C = ( /t )*A).
2. Fringing capacitance to substrate.
3.Coupling capacitance between two metal line on the same layer.

An empirical formula

C = [(

w
w
t
) + 0.77 + 1.06( )0 .25 + 1.06( )0 .5 ]
h
h
h

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.3.5.2 Multiple Conductor Capacitance

Figure 4.11 shows a model for routing

structure with multiple conductances.

The capacitance of the middle layer (conductor of interest ) is divided into three components.
1. The line-to-ground capacitance.
2. The line-to-line capacitance.
3. The crossover capacitance.

Figure 4.12 shows the capacitance of

middle layer 2 to ground C2= C21 + C23 + C22.

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Empirical formulas to compute these capacitance values are given in Weste text book.

Figure 4.13 shows various capacitances for a two-level-metal process.

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Chapter 4:Circuit Characterization and Performance Estimation

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4.3.6 Distributed RC Effects

The propagation of a signal along a wire depends on many factors, including the distributed resistance and
capacitance of the wire, the impedence of the driving source, and the load impedence.

A long wire can be represented in terms of several RC sections, as shown in Figure 4.15.

The response a node Vj with respect to time is given by C

2
when expressed as a differential form: rc dV = d V2
dt
dx
where x = distance from input

r = resistance per unit length

c = capacitance per unit length.

dV j
dt

= ( I j 1 I j ) =

V j 1 V j
R

V j V j +1
R

Chapter 4:Circuit Characterization and Performance Estimation

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The solution for the propagation of a voltage step along a wire of length x shows that the rise/fall delay
tx = k x2 , where k is a constatnt.

Alternatively, a discrete analysis yields a signal delay of t n = 0.7 *

2
sections. As n becomes very large, t l = 0.7 rcl 2

RCn(n + 1)
, where n is the number of
2

where r = resistance per unit length.

c = capacitance per unit length.
l = length of wire.

Figure 4.16 shows an example of using the above formula to insert a buffer on a long wire
without a buffer, the propagation delay tp = 0.7 * 20 * 4 *10-4 * 20002 /2= 112ns
with a buffer on the middle, tp = (2 * 0.7 * 20 * 4 *10-4 * 10002 )/2+ tbuf =66ns + tbuf

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

Note that the above calculation considers only propagating a voltage step signal along the wire.

A model for the distributed RC delay, which takes driver and receiver loading into account is shown in
Figure 4.17, where
Rs = the output resistance of the driver.
Ci = the receiver input capacitance.
Rt = the lumped resistance of the wire.
Ct = the lumped capacitance of the wire.

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Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.3.7 Capacitance Design Guide

Table 4.6 gives respresentative capacitance value (no fringing) for a 1 m n-well COMS process.

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Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

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Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.3.8 Wire-length Design Guide

For sufficiently small wire length, the wires RC delay can be ignored (i.e., the delay element in Figure
4.17 can be removed) and thus the wire can be modeled as a simple capacitive load.

To model a wire as a simple capacitive load, the wires RC delay w and gate delay g must satisfy:
2 g
1
w << g rcl 2 << g l <<
2
rc
For example, assume g = 200ps and for a minimu-width aluminum wire

l <<

2* 0.2*10 9
0.05 *30* 10 18

16000

where r = 0.05 /
c = 30 * 10-18 F/

= is the value of - design rule

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Chapter 4:Circuit Characterization and Performance Estimation

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4-27

Table 4.7 shows the maximum interconect length for a typical CMOS proces in terms of such that a wire
can be modeled as a simple capacitive load. This table assumes gate delays of the order of 100ps to 500 ps.

Chapter 4:Circuit Characterization and Performance Estimation

Rung-Bin Lin

4.4 Inductance

On-chip inductances are small, but bond-wire inductances are large enough to cause troubles for I/O
circuits(voltage spike dV = L

dI
).
dt

For an on-chip conductor whose inductance is L = ln ( 8h + w ) .

w 4h
2
where w = the width of the conductor
h = the height above the substrate.
For bond-wire inductance L = ln( 4h ).
2
d
where = permeability of the wire
h = the height above the ground plane
d = the diameter of the wire.

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Chapter 4:Circuit Characterization and Performance Estimation

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4.5 Switching Characteristics

Referring to Figure 4.18, some timing parameters are defined as follows:

Rise time, tr = time for a waveform to rise from 10% to 90 % of its steady-state value.
Fall time, tf = time for a waveform to fall from 90% to 10% of its steady-state value.
Delay time, td = time difference between input transition(50%) and the 50% output level.
Output rising delay time, tdr = the delay time of a rising output in response to the input change.
Output falling delay time, tdf = the delay time of a falling output in response to the input change.

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Chapter 4:Circuit Characterization and Performance Estimation

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4.5.1 Analytic Delay Models

4.5.1.1 Fall Time

Referring to Figure 4.18, initially the n-device is cut-off and the load capacitor CL is charged to VDD (at
point X1 on the characteristic curve). Application of a step voltage (i.e. Vgs = VDD) at the input of the
inverter changes the operating point to X2. From this onward, the operating point moves toward X3. Thus,
it is evident that the fall time tf consists of two intervals :
1. tf1 = period during which the capacitor voltage Vout drops from 0.9 VDD to (VDD-Vtn). Equivalent
circuit is shown in Figure 4.19(a).
2. tf2 = period during which the capacitor voltage Vout drops from (VDD-Vtn) to 0.1 VDD.

Rung-Bin Lin

Chapter 4:Circuit Characterization and Performance Estimation

During tf1, the n-device is in saturation, thus

dV

C L out = n (VDD Vtn ) 2

solving this equation for t, we obtain
dt
2
t f1 =

2C L (Vtn 0.1VDD )
n (VDD Vtn ) 2

During tf2, the n-device is non-saturated, thus C L

Solving this equation, we obtain t f 2 =

tf = tf1 + tf 2 =

dVout
1 2
. out )
= n ((VDD Vtn )Vout V
dt
2

CL
ln(19 20n) , where n = Vtn
nVDD (1 n)
VDD

2C L
(n 0.1 ) 1

+ ln ( 19 20n)

nVDD( 1 n) ( 1 n) 2

that is, t f k

CL
where k = 3~4.
nVDD

tf CL, tf 1/VDD and tf

(4.37)

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Chapter 4:Circuit Characterization and Performance Estimation

4.5.1.2 Rise Time

Due to the symmetry of the CMOS circuit, t r =

where p =

Vtp
VDD

. As before,

tr 3 4

CL
pVDD

2C L

p 0.1 1
+ ln(19 20 p )

pVDD (1 p ) 1 p
2

(4.39)

For equally sized n- and p-transistors, where n = 2 p , t f =

For equal rise and fall time,

tr
2

n
= 1. This implies w p = 2 ~ 3wn , where wp is the channel width of the pp

device and wn is the channel width of the n-device.

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4.5.1.3 Delay Time

In most CMOS circuits, the delay of a single gate is dominated by the output rise and full times. It is

tr
t
and t df = f .
2
2
t + t dr t r + t f
The average gate delay for rising and falling transition is t av = df
.
=
2
4
Figure 4.20 illustrates a SPICE simulation of a step input applied to an inverter driving a capacitive load.

approximated by t dr =

With Vtn = .767V , Vtp = .938V , = 4.04 10 4 , = 3.48 10 4 , VDD = 5.0V , C L = 0.5 pF.
n
p
By Eq.(4.39), t r = 1.04ns (compared to 1.14ns from SPICE)
By Eq.(4.37), t f = 0.83ns (compared to 0.89ns from SPICE)
t
t dr = r = 0.502ns (compared to 0.52ns by SPICE)
2
tf
t
=
= 0.41ns (compared to 0.45ns by SPICE).
df

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Chapter 4:Circuit Characterization and Performance Estimation

Alternatively, the output fall delay time can be approximated by t df = AN

process-specific constant and derived as AN =

CL

(i.e., Rn =

2(1 n) VO
1
2n
+ ln(
)

VDD (1 n) 1 n
VO

AN

4-34

). AN is a

where n = Vtn
VDD

and VO = Vout .
VDD
Vtp
1
2p
2(1 + p ) VO
C
L
A
p
=
+
ln
=
<0 .

Similarly, t dr = Ap
( E.Q. 4.47) and p
1 + p
where
(
1
+
)
V
p
V
V

DD
O
DD

4.5.2 Empirical Delay Models

A circuit simulator is employed to find the timing parameter of interest and the coefficient of some delay
equation is derived. For example, the coefficients AP and AN can be found by
Ap = t dr spice

p
CL

= 0.52 10 9

3.48 10 4
= 0.36 (0.31 calc)
0.5 10 12

4.04 10 4
= 0.45 10
AN = t df spice
= 0.36 (0.29 calc)
12
0.5 10
CL
Note that the values of tdr-spice and tdf-spice are obtained from SPICE simulation.
9

Thus, t dr = 0.36 C L and t df = 0.36 C L for the gates with W = 2W .

p
n

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Chapter 4:Circuit Characterization and Performance Estimation

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4.5.3 Gate delays

The delay of simple gate may be approximated by constructing an equivalent inverter. The pull-down ntransistor and pull-up p-transistor of the equivalent inverter are of a size to reflect the effective strength of
the real pull-down or pull-up in the gate.

For example, the equivalent inverter for the 3-input NAND gate shown in Figure 4.21 has the effective
of the n-transistor as neff = 1

n1

For n1 = n 2 = n 3 , = n
neff
3

1
1

n2

n3

Chapter 4:Circuit Characterization and Performance Estimation

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For the pull-up case, only one p-transistor has to turn on to raise the output. Thus, peff = p.
tr
CL
CL
1 .
For p = 0.3 n , t r = k
,
. Thus
tf = k
t

0.3 nVDD
f
n
VDD
3

More clearly, for a series of 3 n-transistor, series = n

3

In general, the fall time is mtf for m n-transistors in series; the rise time for m p-transistor in series is mtr.

The fall (rise) time for a parallel connection of n(p)-transistors is tf/m (tr/m) for m transistors in parallel, if
all the transistors are turned on simultaneously.

Chapter 4:Circuit Characterization and Performance Estimation

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4.5.4 Further Delay Topics

4.5.4.1 Input Waveform Slope

The analytical delay expression in an inverter presented in the previous section was derived based on the
assumption that the input waveform is a step function. However, the real input waveform has a finite slope
that will modify the delay of a gate.

Figure 4.23 shows the influence of input waveform on the delay time of an inverter based on SPICE
simulation.The results are tabulated in Table 4.8.

Rung-Bin Lin

Chapter 4:Circuit Characterization and Performance Estimation

The following modification to the output rising delay is made to consider the input waveform slope:
t dr = t dr step +

tinput fall

(1 2 p ) , p =

Vtp

<0
6
VDD
where tdr-step = the output rising delay due to a step input calculated in EQ. 4.47 .

tinput-fall = the input fall time

Similarly, t df = t df step +

tinput rise
6

(1 + 2n) for n =

These two equations are valid only when

Vtn
>0 .
VDD

tinput fall nVDD

CL

<

tinput fall nVDD

6p
6n
<
and
.
3
(1 p )
CL
(1 n) 3

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4.5.4.2 Input Capacitance

The input capacitance is in fact a function of gate voltage. (i.e., it is not a constant)

An effect known as bootstrapping can also modify the effective input capacitance of a logic gate.

As shown in Figure 4.24(a), in the case where the input is rising (that is, the output is high), the effective
input capacitance is Cgs+Cgd.When the output starts to fall, the voltage across Cgd increases, requiring the
input to supply more current to charge Cgd. This effect is seen in Figure 4.24(b).

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4.5.4.3 Switch Level Models

A switch model represents a transistor as a resistance for charging or discharging a capacitance is shown
in Figure 4.25.

A variety of timing models have developed to estimate the delay of logic gates:
Simple RC model: the total resistance of pull-up or pull-down path is calculated and all the
capacitance of nodes are lumped onto the output of the gate.
For the example shown in Figure 4.26.,

t df = R pulldown C pulldown path = ( RN 1 + RN 2 + RN 3 + RN 4 ) (Cout + Cab + Cbc + Ccd )

, while for the rise delay tdr = Rp4 * Cout. This is a pessimistic model.

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Penfield-Rubenstein Model: was developed to calculate delays in generalized RC trees. t d = i Ri Ci

for a group of series transistors. Where Ri is the summed resistance from point i to power or ground
and Ci is the capacitance at point i.
For example, for the gate shown in Figure 4.26,

t df = RN 1 * Ccd + ( RN 1 + RN 2 ) * Cbc + ( RN 1 + RN 2 + RN 3 ) * Cab + ( RN 1 + RN 2 + RN 3 + RN 4 ) * Cout

Penfield-Rubenstein Slope Model: widely used in transistor-level-timing analyzers. See the textbook
for details.

Chapter 4:Circuit Characterization and Performance Estimation

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4.5.4.4 Macromodeling

To derive a set of accurate formulae to calculate gate capacitance and logic gate behavior based on the
device equation.

Figure 4.28 shows a typical model along with the timing model, where tswin is the input waveform, tswout is
the output waveform, Cin is the input capacitance, and CL is the output capacitance.

Another commonly used approach in ASIC community treats logic gates as simple delay elements. Each
gate type is simulated with a circuit simulator to derive an equation to compute the delay of a particular
gate: td = tinternal + k* toutput, where tinternal is a fixed delay when no load is attached; k is the output loading;
toutput is the output delay per output loading.

Chapter 4:Circuit Characterization and Performance Estimation

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Figure 4.29 shows a typical SPICE circuit used to calibrate delay equation.

Table 4.9 summarizes the data.

Thus for the gate shown in Figure 4.29, tdr = (0.255 + k * 2.12) ns, tdf = (0.42 +k *3.82) ns

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4.5.4.5 Body Effect

Body effect is the term given to the modification of the threshold voltage, Vt, with a voltage difference
between source and substrate.

Vt r Vsb , where r is a constant, Vsb is the voltage between source and substrate, and Vt is the
change in threshold voltage.

For the example shown in Figure 4.30(a), the n-transistor at the output will switch slower if the source
potential of this transistor is not the same as the substrate.

In the upper NAND gate the lower transistors are initially turned on while transistor N4A is turned off. The
result is seen in Figure 4.30(b) in the form of waveform CD when the input on N4A rises.

In the lower NAND gate, the upper transistors are turned on initially, while transistor N1B is turned off.
(Effectively, the Vsb of the upper transistors is not equal to zero). The result is seen in Figure 4.30(b) when
N1B turns on, which indicates the output transition lags behind 0.4 ns.

Two strategies to offset the body effect:

Place the transistors with the latest arriving signals nearest the output of a gate.
Minimize the capacitance of internal nodes.

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4.6 CMOS-Gate Transistor Sizing

4.6.1 Cascaded Complementary Inverters

Previously discussed, we must take Wp = (23) Wn to approximately equalize the rise and fall times of an
inverter. However, in some cascaded structures it is possible to use minimum or equal-sized devices to
achieve the same result.

For example, as for the circuit shown in Figure 4.31(a), with Wp = 2Wn ,

R
tinv pair t fall + t rise R3Ceq + 2 3Ceq = 3RCeq + 3RCeq = 6 RCeq
2

where R is the effective ON resistance of a unit-sized n-transistor (W=2, L=1), and Ceq = Cg+Cd is the
capacitance of a unit-sized gate and drain region. As for the case shown in Figure 4.31(b) with Wp = Wn,

t inv pair t fall + t rise R 2Ceq + 2 R 2Ceq = 6 RCeq

Chapter 4:Circuit Characterization and Performance Estimation

Also note that changes in the ratio affect the inverter logic threshold voltage Vinv, which directly
influences the delay of output response. From equation (2.2),

VDD + Vtp + Vtn

Vinv =
1+

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n
p

n
p

Table 4.10 summarizes Vinv for a range of its constituent parameters.

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4.6.3 Stage Ratio

A chain of increasingly larger inverters is usually employed to drive large loads. The ratio by which each
stage is increased in size is called the stage ratio.

Considering the circuit shown in Figure 4.33, inv-1 is a minimum-sized inverter driving inv-2, which is a
times the size of inv-1. Similarly, the size of inv-3 is a times the size of inv-2 (that is, inv-3 is a2 the size of
inv-1).

The delay through each stage is atd, where td is the average delay of a minimum-sized inverter driving
another minimum-sized inverter. Hence the delay through n stages is natd. If the ratio of the load
capacitance to the capacitance of a minimum-sized inverter is R=CL / Cg , then R = an. Hence ln(R)=nln(a).
Thus,

Total delay = nat d =

ln( R)
at d
ln(a)

The variable part of the above equation, normalized to e, is graphed in Figure 4.33(b). The graph shows
when a = 2.7 = e would minimize the total delay.

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4.7 Power Dissipation

Two components of CMOS power dissipation:

Static dissipation due to leakage current.
Dynamic dissipation due to switching transient current and charging/discharging of load capacitance.

4.7.1 Static Dissipation

For the inverter shown in Figure 3.34, if the input is either at one of its steady-state logic values (0 or 1),
there is no direct path from VDD to VSS . Thus no static power Ps dissipates, theoretically.

However, some small static dissipation actually exists due to:

Reverse biased leakage between diffusion regions and the substrate.
Subthreshold conduction (i.e. Vin < Vt )

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The leakage current between diffusion and substrate can be explained by the model shown in Figure 3.35.
The diodes in the model are reverse-biased and the leakage current is described by diode equation.

io = is (e qV
Where

kT

1)

i s = reverse saturation current

V = diode voltage
q = electronic charge (1.602*10-19 C)
K = Boltzmanns constant (1.38*10-23 J/K)
T = temperature

Chapter 4:Circuit Characterization and Performance Estimation

The leakage current per device ranges from 0.1nA to 0.5nA.

Total static power dissipation Ps can be obtained by

n

Ps = leakage current * supply voltage

1

where n = number of devices.

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4.7.2 Dynamic Dissipation

Consists of short circuit power and load capacitance charging/discharging power.

Short circuit dissipation is due to existence of a direct path from VDD to VSS when the output changes either
from 1 to 0 or 0 to 1.

Short circuit dissipation depends on the input rise/fall time, the load capacitance and gate design.

Fig 4.36 depicts a scenario about how output loading could influence the short circuit current.

The average dynamic power Pd dissipated during switching for a square-wave input, Vin, having a
repetition frequency of fp=1/tp is given by
1 tp
1 t
Pd = 02 in (t )Vout dt + t pp i p (t )(VDD Vout )dt
tp
tp 2
For a step input and with in (t ) =

C L dVout
,
dt
2

C V
C 0
CV
2
Pd = L 0 DD Vout dVout + L VDD (VDD Vout )d (VDD Vout ) = L DD = C LVDD f p
tp
tp
tp

Dynamic power dissipation can be limited by reducing supply voltage, output capacitance and the
switching frequency.

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Chapter 4:Circuit Characterization and Performance Estimation

4.7.3 Short-circuit Dissipation

For an inverter without load, assuming tr=tf=trf, the short circuit power dissipation (detailed derivation can
be found in Weste textbook).
Psc =

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12

(VDD 2Vt ) 3

t rf
tp

4.7.4 Total Power Dissipation

Ptotal=Ps+Pd+Psc

More realistic situation, the dynamic power Pd should be calculated as follows:

Percentage activity* CTotalVDD
Pd =
,
tp
2

where percentage-activity is a ratio between the estimated number of switchings and the number of
clock cycles during a certain period of time.

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4.8 Sizing Routing Conductors

Metal power-carrying conductors have to be sized for three reasons:

Metal migration (electro-migration)
Power supply noise and integrity ( i.e., satisfactory power and signal voltage levels are presented to
each gate.)
RC delay

Metal migration is the transport of metal ions through a conductor. It may cause breakage or deformation
of conductor.

Factors that influence the electro-migration rate are:

Current density, as a rule of thumb, 0.4 mA/um to 0.1 mA/um of metal width should be used for both
VDD and VSS lines.
Temperature
Crystal structure

Existence of substantial resistance on supply or ground line would cause considerable IR drop (power drop
and ground bounce) during charging transients. This directly reduces the noise margin of gates and causes
incorrect operation of gates.

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4.8.1 Power Drop and Ground Bounce

For a clocked synchronous system, the output transitions of the gates are made close to the clock transition.
Thus, a large current spike would appear on power or ground bus. This would effectively reduce the noise
margin. (see the following figure)

Ip

Rp

transistor
network

Ig

Rg

VDD-inv = VDD - Ip*Rp

Vout

VSS-inv = Ig*Rg

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4.8.2 Contact Replication

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For a very wide conductor to connect to another layer, an array of small contacts, suitably spaced,
generally provides just as much current-carrying capacity as a single long, narrow contact. (see Figure
4.38)

4.9 Charge Sharing

In many structures a bus can be modeled as a capacitor Cb as shown in Figure 4.39. Sometimes the voltage
on this bus is sampled (latched) to determine the state of a given signal. Charge sharing thus occurs.

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For a successful sampling, the resultant voltage VR (not shown) should be correctly reflect the state of the
bus. For example,Qb=CbVb, Qs=CsVs, QT=CbVb+CsVs, CT=Cb+Cs, Thus VR=QT/CT=(CbVb+CsVs)/(Cb+Cs),
if Vb=VDD (the bus is in state 1), and Vb>>Vs , then VR=VDD[Cb/(Cb+Cs)]. For a successful sampling,
Cs<<Cb. This results in VR VDD .

Example:

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Chapter 4:Circuit Characterization and Performance Estimation

4.10 Design Margining

The circuit behavior can be affected by the variation of operating conditions and manufacturing process.
These variations include:
operating temperature variation
supply voltage variation
process variation

4.10.1 Temperature Variation

As the temperature is increased, the drain current is

reduced. This variation is shown in Figure 4.40.

The temperature variation requirement for different applications is shown as follows:

Application

Temperature
o

Commercial
Industrial
Military

Min ( C)
0
-40
-55

Max(oC)
70
85
125

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The die temperature is specified as follows: Tj = Ta +Qja * Pd

where Tj = the junction temperature in oC (temperature of the chip itself)
Ta = the ambient temperature in oC (temperature of surrounding air)
Qja = the package thermal impedance, expressed in oC/watt
Pd = the power dissipation

4.10.2 Supply Voltage Variation

For example, if Qja = 30 oC/watt, Pd = 1 watt, and Ta = 85 oC, then Tj = 115 oC.

When specifying a part, a variation of 10 % (normally) on the supply voltage accompanies the data sheet.

4.10.3 Process Variation

The variation in device characteristics due to process variation follows a normal distribution as shown in
Figure 4.41.

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The variations in device performance can be caused by variations in doping density, implant dose, and
variations in the width and thickness of active diffusion and oxide layers and passive conductors.

When considering the influence of process variation on the transistor speed, the following terms are used:
nominal(typical)
fast
slow

There are four types of boundary conditions for two types of transistors:

Fast-n and fast-p

Fast-n and slow-p
Slow-n and fast-p
Slow-n and slow-p

If the gains of the p- and n-transistors track but the threshold voltage is not, the following process corners
can be observed:
Slow-n and low-Vtp
Low-Vtn and slow-p

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10.10.4 Design Corners

A design corner refers to an imaginary box that surrounds the guaranteed performance of the transistors.

The worst-power or high-speed corner: fast-n and fast-p process corner combined with the lowest
operating temperature and the highest operating voltage.

The worst-speed corner: slow-n and slow-p process corner combined with the highest operating
temperature and the lowest operating voltage.

The worst-speed corner can be used to check external setup times while the highest speed corner can be
used to check hold time constraints.

Table 4.11 shows a list of checks performed for a CMOS digital system.

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4.10.5 Packaging Issues

Selection of package must consider the thermal impedance of the package and the inductance of package
pins.

The thermal impedance is a measure of the effectiveness with which a package can conduct heat away
from the die.

Figure 4.42 shows some typical packages.

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4.11 Yield

The yield is influenced by such factors as:

technology
chip area
layout

Yield is defined as Y= (No. of good chips on wafer) / (Total number of chips)

4.12 Reliability

The potential reliability of a CMOS chip:

Hot electron effects

Electro-migration
Oxide failure
Die temperature
ESD protection.

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4.13 Scaling of MOS-transistor Dimensions

Scaling: to shrink the size of physical dimensions or to scale the property values of a transistor by a
dimension factor .

Three types of scaling:

Constant field scaling: involve scaling of all
physical dimensions (including those vertical
to surface), device voltages and the
concentration densities.
Constant voltage scaling: where VDD voltage is
kept constant, while the process is scaled.
Lateral scaling: where only gate length is scaled.

The resultant effect of these three types

of scaling is shown in Table 4.12.

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4.13.2 Interconnect-Layer scaling

Scaling of interconnect could result in changes of interconnect resistance and capacitance.

For example, scaling the thickness and width of a conductor by ,the scaled-line resistance R is given by
L
L
]=
[
] = R,
W t W
where = conductivity
R ' = R s '[

Rs ' =

is sheet resistance of the scaled-line

t

t = conductor thickness before scaling

The voltage drop along the scaled-line for a constant field scaling is

I
Vd ' = ( )(R ) = IR

The line-response time is

C
t s ' = (R )( ) = RC

Chapter 4:Circuit Characterization and Performance Estimation

The influence of scaling on interconnect, if the interconnect is scaled by and the current is increased
by , is summarized in Table 4.13.

4.13.3 Scaling in Practice

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As it can be seen from Table 4.14, constant voltage scaling has been used in the past.

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4.14 Summary

resistance, capacitance, inductance calculations

delay estimation

power estimation

design margining and reliability

effect of scaling

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