Figure 5-1 Components of an SM Chart

optional
state code
xxx
state_name/
output list
(a) state box

(true
branch) 1

condition

(false
0 branch)

(b) decision box

conditional
output list
(c) conditional
output box

Figure 5-2 Example of an SM Block

one entrance path

S1 / Z1 Z2 one state

link
path a

SM
block

1
X1
link
path b

Z3 Z4
0
0

1
X2

X3

Z5
2

3
n exit paths

Figure 5-3 Equivalent SM Blocks

S1 / Z1

S1 / Z1
0

X1

X2

Z2

X1

X1

0
0

S2 /
(a)

X2

S3 /

Z2

Z2

S2 /

S3 /
(b)

Figure 5-4: Equivalent SM Chart for a Combinational Network

S0 /
S0 /

A+BC
0

0
1

C
Z1

1
B

0
Z1

(a)

(b)

Figure 5-5 SM Block with Feedback

S0 /
0

X
1

(a) incorrect

S0 /
0

X
1

(b) correct

Figure 5-6 Equivalent SM Blocks

S0 / Z1
1
X1

S0 / Z1
Z2
1

1
X1

1
X2

X3

1
X2

Z2

Z3

Z4

0
Z3

(a) Parallel form

1
Z4

X3
0

(b) Serial form

Figure 5-7 Conversion of State Graph to an SM Chart

00
S0 / Za

S0
Za

Link 1
0

1/0
0/0

0/0

0/Z1

01
S1 / Zb

Link 2
0

1
S2 / Zc 11
Link 3
0
Z1

S1
Zb

1
Z2

1/0

1/Z 2
S2
Zc

Figure 5-8 Timing Chart for Figure 5-7

Clock
State
X
Za
Zb
Zc
Z1
Z2

S0

S1

S2

S2

S0

S0

Figure 5-9 SM Chart for Binary Multiplier

S0 /
0

St

Load
S1 /
0

Sh

Ad

S2 / Sh

1
S3 / Done

Figure 5-10(a) VHDL for SM Chart of Figure 5-9

entity Mult is
port(CLK,St,K,M: in bit;
Load,Sh,Ad,Done: out bit);
end mult;
architecture SMbehave of Mult is
signal State, Nextstate: integer range 0 to 3;
begin
process(St, K, M, State)
-- start if state or inputs change
begin
Load <= '0'; Sh <= '0'; Ad <= '0';
case State is
when 0 => if St = '1' then
-- St (state 0)
Load <= '1'; Nextstate <= 1;
else Nextstate <= 0;
-- St'
end if;
when 1 => if M = '1' then
-- M (state 1)
Ad <= '1'; Nextstate <= 2;
else
-- M'
Sh <= '1'; if K = '1' then Nextstate <= 3; -- K
else Nextstate <= 1;
-- K'
end if;
end if;
when 2 => Sh <= '1';
-- (state 2)
if K = '1' then Nextstate <= 3;
-- K
else Nextstate <= 1;
-- K'
end if;

Figure 5-10(b) VHDL for SM Chart of Figure 5-9

when 3 => Done <= '1';
Nextstate <= 0;
end case;
end process;
process(CLK)
begin
if CLK = '1' then
State <= Nextstate;
end if;
end process;
end SMbehave;

-- (state 3)

-- update state on rising edge

Figure 5-11 Block Diagram for Dice Game

Display

Display

1-to-6
Counter

1-to-6
Counter

DiceGame Module

Reset

Adder
Sum
Point
Register

Comparator

Rb

Roll

Test
Logic

D7
Control
D711
D2312
Eq
Sp

Win

Lose

Figure 5-12 Flowchart for Dice Game

Roll dice

Sum =
7 or 11

Sum =
2,3,or 12

Store sum in
point register
Roll Dice

Sum =
Point

N
N
Sum = 7

Y
Win
Lose

Reset

Reset

Figure 5-13 SM Chart for Dice Game

S0 /
0

S4 /

Rb

1
Roll

S1 /

S5 /

Roll
1

Rb
1

0
1

D2312

1
1

Reset

Eq
0
D7

0
1

Rb
0

D711
0

S2 / Win

Rb

Sp

S3 / Lose
0

Reset

S2 / Win
1

1
S3 / Lose

Figure 5-14 State Graph for Dice Game Controller

Rb'/0

S0

Reset/0

Reset/0
Rb/Roll

Rb/0

Reset'/0

S2

Rb'D 711/0

Win
Reset'/0

S1

Rb'D '711D '2312 /Sp

Rb'D'711D2312 /0 Lose

S4

Rb'/0
Rb'Eq/0

S3

Rb/0

Rb'Eq'D'7 /0

S5
Rb/Roll

Rb'Eq'D 7/0

Figure 5-15(a) Behavioral Model for Dice Game

entity DiceGame is
port (Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end DiceGame;
library BITLIB;
use BITLIB.bit_pack.all;
architecture DiceBehave of DiceGame is
signal State, Nextstate: integer range 0 to 5;
signal Point: integer range 2 to 12;
signal Sp: bit;
begin
process(Rb, Reset, Sum, State)
begin
Sp <= '0'; Roll <= '0'; Win <= '0'; Lose <= '0';
case State is
when 0 => if Rb = '1' then Nextstate <= 1; end if;
when 1 =>
if Rb = '1' then Roll <= '1';
elsif Sum = 7 or Sum = 11 then Nextstate <= 2;
elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3;
else Sp <= '1'; Nextstate <= 4;
end if;
when 2 => Win <= '1';
if Reset = '1' then Nextstate <= 0; end if;

Figure 5-15(b) Behavioral Model for Dice Game

when 3 => Lose <= '1';
if Reset = '1' then Nextstate <= 0; end if;
when 4 => if Rb = '1' then Nextstate <= 5; end if;
when 5 =>
if Rb = '1' then Roll <= '1';
elsif Sum = Point then Nextstate <= 2;
elsif Sum = 7 then Nextstate <= 3;
else Nextstate <= 4;
end if;
end case;
end process;
process(CLK)
begin
if rising_edge(CLK) then
State <= Nextstate;
if Sp = '1' then Point <= Sum; end if;
end if;
end process;
end DiceBehave;

Figure 5-16 Dice Game with Test Bench

Rb
Reset
GameTest

CLK
Sum
Roll
Win
Lose

DiceGame

Figure 5-17 SM Chart for Dice Game Test

T0 / Rb
0

0
Roll
1

Sum = Sumarray(i)
i=i+1
T1 /
T2 /
0

i>N

Win or
Lose
1
Reset

T3 / (Stop)

Figure 5-18(a) Dice Game Test Module

entity GameTest is
port(Rb, Reset: out bit; Sum: out integer range 2 to 12;
CLK: inout bit; Roll, Win, Lose: in bit);
end GameTest;
library BITLIB;
use BITLIB.bit_pack.all;
architecture dicetest of GameTest is
signal Tstate, Tnext: integer range 0 to 3;
signal Trig1: bit;
type arr is array(0 to 11) of integer;
constant Sumarray:arr := (7,11,2,4,7,5,6,7,6,8,9,6);
begin
CLK <= not CLK after 20 ns;

Figure 5-18(b) Dice Game Test Module

process(Roll, Win, Lose, Tstate)
variable i: natural;
-- i is initialized to 0
begin
case Tstate is
when 0 => Rb <= '1';
-- wait for Roll
Reset <='0';
if i>=12 then Tnext <= 3;
elsif Roll = '1' then
Sum <= Sumarray(i);
i:=i+1;
Tnext <= 1;
end if;
when 1 => Rb <= '0'; Tnext <= 2;
when 2 => Tnext <= 0;
Trig1 <= not Trig1;
-- toggle Trig1
if (Win or Lose) = '1' then Reset <= '1'; end if;
when 3 => null;
-- Stop state
end case;
end process;
process(CLK)
begin
if CLK = '1' then
Tstate <= Tnext;
end if;
end process;
end dicetest;

Figure 5-19 Tester for Dice Game

entity tester is
end tester;
architecture test of tester is
component GameTest
port(Rb, Reset: out bit;
Sum: out integer range 2 to 12; CLK: inout bit; Roll, Win, Lose: in bit);
end component;
component DiceGame
port (Rb, Reset, CLK: in bit; Sum: in integer range 2 to 12 ; Roll, Win, Lose: out bit);
end component;
signal rb1, reset1, clk1, roll1, win1, lose1: bit; signal sum1: integer range 2 to 12;
begin
Dice: Dicegame port map(rb1,reset1,clk1,sum1,roll1,win1,lose1);
Dicetest: GameTest port map(rb1,reset1,sum1,clk1,roll1,win1,lose1);
end test;

Figure 5-20 Simulation and Command File for Dice Game Tester
list /dicetest/ trig1 -NOTrigger sum1 win1 lose1 /dice/point
run 2000

ns
0
100
260
420
580
740
900
1060
1220
1380
1540
1700
1860

delta
+0
+3
+3
+3
+2
+3
+2
+2
+3
+2
+2
+2
+3

trig1
0
0
0
0
1
1
0
1
1
0
1
0
0

sum1
2
7
11
2
4
7
5
6
7
6
8
9
6

win1
0
1
1
0
0
0
0
0
0
0
0
0
1

lose1
0
0
0
1
0
1
0
0
1
0
0
0
0

point
2
2
2
2
4
4
5
5
5
6
6
6
6

Table 5-1 PLA Table for Multiplier Control

S0
S1
S2
S3

A
0
0
0
0
0
1
1
1

B St M K A+ B+ Load Sh Ad Done
0 0 0
0
0
0
0
0
0 1 0
1
1
0
0
0
1 0 0 0
1
0
1
0
0
1 0 1 1
1
0
1
0
0
1 1 1
0
0
0
1
0
0 0 0
1
0
1
0
0
0 1 1
1
0
1
0
0
1 0
0
0
0
0
1

A+ = A'BM'K + A'BM + AB'K = A'B(M + K) + AB'K

B+ = A'B'St + A'BM'(K'+K) + AB'(K'+K) = A'B'St + A'BM' + AB'
Sh = A'BM'(K'+K) + AB'(K'+K) = A'BM' + AB'
Load = A'B'St

Ad = A'B M

Done = A B

Figure 5-21 PLA Realization of Dice Game Controller

Rb
Reset
D 711
D7
D 2312
Eq

Win
Lose
Roll
Sp
C+
PLA
C
B

B+
A+

D
CK
D
CK
D
CK

A
Clock

Q
Q
Q

Table 5-2 PLA Table for Dice Game

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

ABC Rb Reset D7 D711 D2312

000 0

000 1

001 1

001 0

0
0
001 0

0
1
001 0

010
0

010
1

011
1

011
0

100 0

100 1

101 0

101 0

101 0

101 1

110

111

Eq A+ B+ C+ Win Lose
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
1
0
1
0
0
0 1
0
0
0
0
0 0
1
1
0
0
1 0
1
0
0
0
1
0
1
0
0

Roll
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1

Sp
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0

Figure 5-22 Maps Derived from Table 5-2

AB

AB
00 01

CRb

11

10

CRb

AB
00 01 11

10

CRb

00 01

11

00

X 1

00

R'

00

01

X 1

01

R'

01

11

X 1

11

R'

11

X E2

10

R'

10

10

E1

E1 = D'711 D'2312
E2 = D'7 Eq'

E3

E4

R = Reset
E3 = D
=D
D'
+ D'
+ D'
711
711 2312
711
2312
+
+
D 7 Eq' = Eq D 7
E4 = Eq

10

Figure 5-23 Data Flow Model for Dice Game

library BITLIB;
use BITLIB.bit_pack.all;
architecture Dice_Eq of DiceGame is
signal Sp,Eq,D7,D711,D2312: bit:='0'; signal DA,DB,DC,A,B,C :bit:='0';
signal Point: integer range 2 to 12;
begin
process(Clk)
begin
if rising_edge(Clk) then
A <= DA; B <= DB; C <= DC;
if Sp = '1' then Point <= Sum; end if;
end if;
end process;
Win <= B and not C;
Lose <= B and C;
Roll <= not B and C and Rb;
Sp <= not A and not B and C and not Rb and not D711 and not D2312;
D7 <= '1' when Sum = 7 else '0';
D711 <= '1' when (Sum = 11) or (Sum = 7) else '0';
D2312 <= '1' when (Sum = 2) or (Sum = 3) or (Sum = 12) else '0';
Eq <= '1' when Point=Sum else '0';
DA <= (not A and not B and C and not Rb and not D711 and not D2312) or
(A and not C) or (A and Rb) or (A and not D7 and not Eq);
DB <= ( (not A and not B and C and not Rb) and (D711 or D2312) )
or (B and not Reset) or ( (A and C and not Rb) and (Eq or D7) );
DC <= (not B and Rb) or (not A and not B and C and not D711 and D2312) or
(B and C and not Reset) or (A and C and D7 and not Eq);
end Dice_Eq;

Figure 5-24 Counter for Dice Game

entity Counter is
port(Clk, Roll: in bit;
Sum: out integer range 2 to 12);
end Counter;
architecture Count of Counter is
signal Cnt1,Cnt2: integer range 1 to 6 := 1;
begin
process (Clk)
begin
if Clk='1' then
if Roll='1' then
if Cnt1=6 then Cnt1 <= 1; else Cnt1 <= Cnt1+1; end if;
if Cnt1=6 then
if Cnt2=6 then Cnt2 <= 1; else Cnt2 <= Cnt2+1; end if;
end if;
end if;
end if;
end process;
Sum <= Cnt1 + Cnt2;
end Count;

Figure 5-25 Complete Dice Game

entity Game is
port (Rb, Reset, Clk: in bit;
Win, Lose: out bit);
end Game;
architecture Play1 of Game is
component Counter
port(Clk, Roll: in bit;
Sum: out integer range 2 to 12);
end component;
component DiceGame
port (Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end component;
signal roll1: bit;
signal sum1: integer range 2 to 12;
begin
Dice: Dicegame port map(Rb,Reset,Clk,sum1,roll1,Win,Lose);
Count: Counter port map(Clk,roll1,sum1);
end Play1;

Figure 5-26 Control Network Using an input Mux

to Select the Next State

PLA or ROM or PAL

TEST

Register

NSF

NST

Inputs

...

MUX

MUX

OUTPUT

Figure 5-27(a) SM Chart with Moore Outputs and One Test per State

S0 /

Rb

0000
1

S1 / Roll

0001
0

Rb

S11 /

1
S2 / Win

D711

0010

0
S12 /

0100
0

Reset

To S13
1

D
D2312

0011
1

To S3

Figure 5-27(b) Chart with Moore Outputs and One Test per State
S13 / Sp

0101
S3 / Lose

S5 / Roll

Rb

Rb

0110

0111

S4 /

Reset

To S0

1000
0
1001
S51 /

Eq
1

0
1010
S52 /

To S2

D7
1

Figure 5-28 MUX for SM Chart of Figure 5-27

Rb
D711
D2312
Eq
D7
Reset

0
1
2
3
4
5
6
7

MUX

TEST

Table 5-3 PLA/ ROM Table for Figure 5-27

State ABCD TEST NSF

NST ROLL Sp Win Lose

S0

0000 001 0000

0001

S1

0001 001 0010

0001

S11

0010 010 0011

0100

S12

0011 011 0101

0110

S2

0100 110 0100

0000

S13

0101 xxx 0111

0111

S3

0110 110 0110

0000

S4

0111 001 0111

1000

S5

1000 001 1001

1000

S51

1001 100 1010

0100

S52

1010 101 0111

0110

Figure 5-29 Control Network Using a Counter

for the State Register

PLA or ROM or PAL

Counter

TEST

Data Load Count

Inputs

...

Next
state
(true)

MUX

Load/Count'

NST

OUTPUT

Figure 5-30(a) SM chart with Serial State Assignment and Added X-states

S0 /
01

Rb'

0000
10

S1 / Roll

0001
0

Rb

S11 /

1
S2 / Win

01

Reset'
10

D711

0010

0
S12 /

1111

0
To S13

D2312

0011

1
To S3

Figure 5-30(b) SM Chart with Serial State Assignment and Added X-state
S13 / Sp 0100

S4 /
10

Rb'

S3 / Lose
1001

0101

Reset'

01

01

10
S5 / Roll 0110
1

Rb

To S0
0111
S51 /

To S2

Sx /

Eq

0
1000
S52 /

D7'

01
10

1010

Figure 5-31 MUX for SM chart of Figure 5-30

Rb'
Rb
D711
D2312
Eq
D 7'
Reset'
1

0
1
2
3
4
5
6
7

MUX

TEST

Load / Count'

Table 5-4 PLA Table for Figure 5-31

State

ABCD TEST

NST

ROLL Sp Win Lose

S0

0000

000

0000

Test(2)

= B C'D' + B C D + A

S1

0001

001

0001

Test(1)

= B'C + B C'D' + A D

S11

0010

010

1111

Test(0)

= A'B'D + B D' + A D'

S12

0011

011

1001

NST(3)

= A'B'C + C D + A D

S13

0100

111

0101

NST(2)

= A'C D' + B + A C'D'

S4

0101

000

0101

NST(1)

= A'C D' + B C

S5

0110

001

0110

NST(0)

= D + A'B'C + B C' + A C'

S51

0111

100

1111

Roll

= A'B'C'D + B C D'

S52

1000

101

0101

SP

= B C'D'

S3

1001

110

1001

Win

= AB

Sx

1010

111

0000

Lose

= A B'D

S2

1111

110

1111

Figure 5-32 SM Charts for Serially Linked State Machine

Machine A
(calling machine)

Machine B
(called machine)
IDLE

SOME
STATES
ZA
1
SA/ZA
0

OTHER
STATES

ZB
1
OTHER
STATES

SB/ZB

Figure 5-33a Linked SM Charts for Dice Game

T0 / En_roll
00
0

01
0

From
Roll Control

Dn_roll

Eq

D 711

T2 / Win

0
10

From
Roll Control

Dn_roll

T2 / Win

To
Roll Control

T1 / En_roll

To
Roll Control

T3 / Lose

D2312

D7

11

0
Reset
1

0
Sp

Reset

(a) Main control

Figure 5-33b Linked SM Charts for Dice Game

S0 /
From
Main Control

En_roll

To
Main Control

Rb
1
S1 /

Dn_roll

Rb

(b) Roll Control

Roll