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Ia1 DPSD

The document is an examination for a Digital Principles and System Design course. It contains 15 multiple choice and written response questions assessing student knowledge of digital logic concepts. Questions cover topics such as logic gate implementation, binary number representation, Boolean algebra, Karnaugh maps, adders/subtractors, and encoders/decoders. Students are instructed to answer all questions in 3 hours, with the exam worth a total of 100 marks.

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Raja Benita
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79 views2 pages

Ia1 DPSD

The document is an examination for a Digital Principles and System Design course. It contains 15 multiple choice and written response questions assessing student knowledge of digital logic concepts. Questions cover topics such as logic gate implementation, binary number representation, Boolean algebra, Karnaugh maps, adders/subtractors, and encoders/decoders. Students are instructed to answer all questions in 3 hours, with the exam worth a total of 100 marks.

Uploaded by

Raja Benita
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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UNITED INSTITUTE OF TECHNOLOGY

Periyanaickenpalayam, Coimbatore- 641 020.


INTERNAL ASSESSMENT EXAMINATION-1(Retest)
FIRST SEMESTER (2014-2015)
Computer Science Engineering
CS 6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN
Time: Three hours Maximum: 100 marks
Answer ALL questions.
PART A (10 2 = 20 marks)
1. Realize OR gate using only NAND gate.
2. Represent the decimal numbers -200 and 200 using 2s complement binary form.
3. Simplify the following Boolean function to a minimum number of literals.
(a) (x+y)(x+y')
4. Using 2s complement perform (42)10 (68)10.
5. Find the complement and dual of F=x(y'z'+yz).
6. Write the truth table of logical AND and XOR gates.
7. What is a Half adder write the truth table.
8. List the modeling techniques available in HDL.
9. Obtain the Boolean functions for the outputs of half subtractor.
10.Implement a full adder with two half adders
PART B (5 16 = 80 marks)
11. (a) Simplify the following Boolean function F using Karnaugh map method .
(i)F(A,B,C,D)=
(ii)F(A,B,C,D)=(0,1,2,4,5,7,11,15).
(iii)F(A,B,C,D)=(2,3,10,11,12,13,14,15).
(iv)F(A,B,C,D)=(0,2,4,5,6,7,8,10,13,15).
(16)
(or)
(b) )(i)Simplify F(A,B,C,D)=(1,4,6,7,8,9,10,11,15) using Quine-McCluskey method. (8)
(ii) State and prove Demorgans theorems and consensus theorems.
(8)
12. (a) (i) Minimize the following expression using K-Map
Y=A'BC'D'+A'BC'D+ABC'D'+AB'C'D+A'B'CD'.
(8)
(ii) Simplify the following function using K-Map technique
f(WXY Z)=
(07891012)+ (2513).
(8)
(or)
(b) Simplify the following function using K-Map technique
(i)G=M(0137911)
(8)
(ii)Simplify F(A,B,C,D)= 0,1,2,5,8,9,10) in sum of products and products of sums using
Kmap.
(8)
13.(a) Simplify the given Boolean function in POS form using K-map and draw the logic
diagram using only NOR gates.F(A, B, C,D)= m (0,1, 4,7,8,10,12, 15)+ d (2, 6,11,14). (16)
(or)
(b) Design a full subtractor with three inputs xy and Bin and two outputs Diff and Bout.The
circuit subtracts x-y-Bin where Bin is the input borrowBout is the output borrow and diff
is the difference.
(16)
14. (a)Draw the schematic of a full adder circuit and give its truth table.
(or)
(b). Explain the gray code to binary converter with the necessary diagram.

(16)
(16)

15. (a) Consider the combinatinal circuit shown in figure


(i)Derive the Boolean expression for T1 through T4.Evaluate the outputs F1 and F2 as a function
of the four inputs.
(ii)Is the truth table with 16 binary combination of the four input variables.Then with the binary
values for T1 through T4 and output F1 and F2 in the table.
(iii)Plot the output Boolean functions obtained in part(ii) on maps and show that simplified
Boolean expression are equivalent to the ones obtained in part(i)
(16)

(or)
(b).Design a binary to gray code converter circuit and BCD to excess -3 code converter
using logic gates.
(16)

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