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314 Processing Unit

This document describes a Verilog module for a processing unit. It contains the description and parameters for registers, buses, multiplexers, an ALU, and other components. The module takes various inputs and outputs the status of registers, buses, and control signals. It implements an 8-bit processor core with 16-bit addressing and includes components like an accumulator, instruction register, program counter, and data handling units.

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P.A. Vinay Kumar
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© © All Rights Reserved
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34 views

314 Processing Unit

This document describes a Verilog module for a processing unit. It contains the description and parameters for registers, buses, multiplexers, an ALU, and other components. The module takes various inputs and outputs the status of registers, buses, and control signals. It implements an 8-bit processor core with 16-bit addressing and includes components like an accumulator, instruction register, program counter, and data handling units.

Uploaded by

P.A. Vinay Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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`timescale 1ns/100ps
//`include "type.v"

module Processing_Unit
#(
parameter word_size = 8,addr_size = 16,op_size = 8,
cnt_size = 4,
DBus_size = word_size, ABus_size = addr_size,
ASize =3
)
(
output [word_size-1:0] instruction,
output [word_size-1:0] DBus_1,DBus_2,DBus_3,
output [addr_size-1:0] ABus,
output [addr_size-1:0] address,
output [word_size-1:0] Reg_ALU,Reg_ACC,
output [addr_size-1:0] Reg_PC,
output [word_size-1:0] Reg_IR,Reg_DB,Reg_DR,Reg_X,Reg_Y,
output [addr_size-1:0] Reg_DAR,Reg_SP,Reg_FLAG,
output [word_size-1:0] D_Bus_out,

// Reg_ROM,Reg_RAM,

output [word_size-1:0] rdout,


input [word_size-1:0] D_Bus,
input [word_size-1:0] rom_word,ram_word,
input [ASize-1:0] rptr,
input
input
input
input
input
input
input
input
input
input

Load_ACC,Inc_ACC,Dec_ACC,
Load_SP,Inc_SP,Dec_SP,
Load_X,
Load_Y,
Load_DAR_XY,
Load_ALU,Load_FLAG,
Load_IR, Load_ALB,
Load_PC_H,Load_PC_L, Inc_PC, Dec_PC,
Load_DAR_L,Load_DAR_H,
Load_DR,Load_DB,Reset_Vector,

input
input
input
input
input

Sel1_ALU,
Sel1_PC1, Sel1_PC2, Sel1_DAR1, Sel1_DAR2,
Sel1_ACC, Sel1_IR,
Sel1_DR,Sel1_DB,
Sel1_SP1,Sel1_SP2,Sel1_X,Sel1_Y,Sel1_ALB,Sel1,

input
input
input
input
input

Sel2_ALU,
Sel2_PC1, Sel2_PC2, Sel2_DAR1, Sel2_DAR2,
Sel2_ACC, Sel2_IR,
Sel2_DR,Sel2_DB,
Sel2_SP1,Sel2_SP2,Sel2_X,Sel2_Y,Sel2_ALB,Sel2,

input Sel3_ALU ,Sel3_ACC,Sel3_IR,Sel3_PC1,Sel3_DAR1,


Sel3_DR,Sel3_DB,Sel3_SP1,Sel3_X,Sel3_Y,Sel3_FLAG,Sel3,

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input Sel4_DAR2, Sel4_PC2, Sel4_SP2,


output N,V,B,D,I,Z,C,

Sel4_DB,

input RWn,
input clk, rst
);
wire alu_zero_flag;
wire [7:0]
opcode = instruction ; // wire [op_size-1:0]
opcode = instruction ;
wire [word_size-1:0] Reg_F;
wire [word_size-1:0] Acc_out,IndexX_out,IndexY_out,DR_out,ALU_out,IR_out,DAR_out1,
SP_out1;
wire [word_size-1:0] DB1,DB2;
wire [addr_size-1:0] PC_out2,DAR_out2,SP_out2;
wire [2**ASize-1:0] Load_R ;
// wire N,V,B,D,I;
// Z;
// ,C ; // from where

wire [word_size-1:0] data_in2;

// for test

assign instruction = Reg_IR;


assign address = ABus;
assign D_Bus_out =DB2;
Reg_Flag FLAG (Reg_F, N,V,B,D,I,Z,C);
defparam FLAG.word_size = word_size;
ALU
ALU1
( Reg_ALU,N,V,B,D,I,Z,C,DBus_1,DBus_2,Reg_ACC,opcode,Load_ALU,
Load_FLAG,clk,rst );
defparam ALU1.word_size = word_size;
Reg_file RegFile ( rdout,DBus_3,rptr,Load_R,RWn,clk,rst
defparam RegFile.DSize=word_size,RegFile.ASize=3 ;

);

Reg_map RegMap (rptr, Load_R);


defparam RegMap.ASize=3 ;
// Accumulator ACC ( Reg_ACC, DBus_1,Load_ACC,Inc_ACC,Dec_ACC,clk,rst);

Accumulator ACC ( Reg_ACC, DBus_3,Load_ACC,Inc_ACC,Dec_ACC,clk,rst);


defparam ACC.word_size = word_size;
Register_Unit IndexX (Reg_X, DBus_3, Load_X, clk, rst);
defparam IndexX.word_size = word_size;
defparam IndexX.Init_Data = 7;
Register_Unit IndexY (Reg_Y, DBus_3, Load_Y, clk, rst);
defparam IndexY.word_size = word_size;
defparam IndexY.Init_Data = 8;
Instruction_Register IR
(Reg_IR, DBus_3, Load_IR, clk, rst);
defparam IR.word_size = word_size;
Program_Counter
PC
(Reg_PC,2'b01,DBus_3,Load_PC_H,Load_PC_L, Inc_PC,
Dec_PC,Reset_Vector,clk, rst);
defparam PC.word_size = addr_size;
defparam PC.OP0=2,PC.OP1=3,PC.OP2=4,PC.OP3=6 ;
Data_Address_Register

DAR

(Reg_DAR,DBus_3,DBus_1,Load_DAR_H,Load_DAR_L,

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Load_DAR_XY, clk, rst);


defparam DAR.word_size = addr_size;
Stack_Pointer SP (Reg_SP,DBus_3,Load_SP,Inc_SP,Dec_SP,Sel1_SP1,Sel1_SP2,clk,rst);
defparam SP.word_size = addr_size;
Data_Register
DR
(Reg_DR, DBus_3, Load_DR, clk, rst);
defparam DR.word_size = word_size;
Data_Buffer
DB (DB1,DB2,Reg_DB,DBus_3,D_Bus,RWn,Load_DB,clk, rst);
defparam DB.word_size = word_size;
Mux_1 Bus1
(
DBus_1,
Reg_ALU,Reg_ACC,Reg_IR,Reg_PC,Reg_DAR,Reg_DR,Reg_DB,Reg_SP,Reg_X,Reg_Y,
Sel1_ALU ,Sel1_ACC,Sel1_IR,Sel1_PC1,Sel1_DAR1,Sel1_DR,Sel1_DB,Sel1_SP1,
Sel1_X,Sel1_Y,Sel1
);
defparam Bus1.word_size = DBus_size;
Mux_1 Bus2
(
DBus_2,
Reg_ALU,Reg_ACC,Reg_IR,Reg_PC,Reg_DAR,Reg_DR,Reg_DB,Reg_SP,Reg_X,Reg_Y,
Sel2_ALU ,Sel2_ACC,Sel2_IR,Sel2_PC1,Sel2_DAR1,Sel2_DR,Sel2_DB,Sel2_SP1,
Sel2_X,Sel2_Y,Sel2
);
defparam Bus2.word_size = DBus_size;

Mux_3 Bus3 // 16bit address on the address bus


(
DBus_3,
Reg_ALU,Reg_ACC,Reg_IR,Reg_PC,Reg_DAR,Reg_DR,Reg_DB,Reg_SP,Reg_X,Reg_Y,
Reg_FLAG,
Sel3_ALU ,Sel3_ACC,Sel3_IR,Sel3_PC1,Sel3_DAR1,Sel3_DR,Sel3_DB,Sel3_SP1,
Sel3_X,Sel3_Y,Sel3_FLAG,Sel3
);
defparam Bus3.word_size = DBus_size; // ABus_size;
Mux_2 Bus4 // 16bit address on the address bus
(
ABus,
Reg_DAR, Reg_PC, Reg_SP, Reg_DB,
Sel4_DAR2, Sel4_PC2, Sel4_SP2 ,Sel4_DB
);
defparam Bus4.word_size = ABus_size; // ABus_size;
endmodule

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