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Control Manual LCD VHDL

This document describes a VHDL entity called "pantalla" that interfaces with an LCD display. It has input ports for an 8-bit data bus, read/write, register select, and enable signals. It also has corresponding output ports that are simply passed through to drive the equivalent signals to control the LCD. The architecture implements the entity by assigning each input port to its corresponding output port, inverting only the enable signal.

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Dan
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141 views

Control Manual LCD VHDL

This document describes a VHDL entity called "pantalla" that interfaces with an LCD display. It has input ports for an 8-bit data bus, read/write, register select, and enable signals. It also has corresponding output ports that are simply passed through to drive the equivalent signals to control the LCD. The architecture implements the entity by assigning each input port to its corresponding output port, inverting only the enable signal.

Uploaded by

Dan
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity pantalla is
port(
DB: in std_logic_vector (7 downto 0);
RW: in std_logic;
RS:
in std_logic;
EN: in std_logic;
LCD_DB: out std_logic_vector (7 downto 0);
LCD_RW: out std_logic;
LCD_EN: out std_logic;
LCD_RS: out std_logic);
end entity pantalla;
architecture codigo of pantalla is
begin
LCD_DB <= DB;
LCD_RW <= RW;
LCD_RS <= RS;
LCD_EN <= not EN;
end architecture codigo;

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