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Exercise No

This document summarizes an exercise to design a D latch and SR latch using Verilog behavioral modeling. It includes the aim to create the sequential circuits in Verilog and verify functionality with a test bench. The document provides the Verilog code for a clocked D latch module and an SR latch module. It also notes that test waveforms will be used to verify the designs.

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Raghunandan Komandur
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16 views

Exercise No

This document summarizes an exercise to design a D latch and SR latch using Verilog behavioral modeling. It includes the aim to create the sequential circuits in Verilog and verify functionality with a test bench. The document provides the Verilog code for a clocked D latch module and an SR latch module. It also notes that test waveforms will be used to verify the designs.

Uploaded by

Raghunandan Komandur
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Exercise No.

13

Latch
Date:
Komandur Raghunandan-RA1412008010032
Type: Sequential design
Aim : To design D latch and SR latch in behavior modeling using
verilog and verify the functionality with test bench.
Simulation tool: ModelSim 10.3
Circuit diagram:

Verilog program:
//Clocked d latch
module d_latch (output reg q,input d,rst,clk);
always@(clk or rst)
if(rst)

q<=1'b0;
else
q<=d;
endmodule
//SR latch
module sr_latch (output reg q,input s,r);
always@(s or r)
case (s,r)
2'b00:q<=q;
2'b01:q<=1'b0;
2'b10:q<=1'b1;
2'b11:q<=1'bx;
endcase
endmodule

Test wave form:


//D latch

//SR latch

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