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Experiment Name: Top-Down Design of VLSI Circuits Using Verilog Hardware Description

This experiment involves designing adders and multiplexers using Verilog HDL at different levels of abstraction. The objectives are to learn Verilog basics, define devices behaviorally and with dataflow, gate-level and switch-level Verilog, simulate and synthesize with Xilinx tools, and generate layouts with Microwind or Electric. 2-1 and 2-2 multiplexers, full adders, and 2-bit full adders are designed and tested at different levels of abstraction with Verilog code, schematics, and output waveforms shown. Issues were encountered getting accurate waveforms from Microwind simulation.

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HasanAlBannaBhuiyan
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40 views

Experiment Name: Top-Down Design of VLSI Circuits Using Verilog Hardware Description

This experiment involves designing adders and multiplexers using Verilog HDL at different levels of abstraction. The objectives are to learn Verilog basics, define devices behaviorally and with dataflow, gate-level and switch-level Verilog, simulate and synthesize with Xilinx tools, and generate layouts with Microwind or Electric. 2-1 and 2-2 multiplexers, full adders, and 2-bit full adders are designed and tested at different levels of abstraction with Verilog code, schematics, and output waveforms shown. Issues were encountered getting accurate waveforms from Microwind simulation.

Uploaded by

HasanAlBannaBhuiyan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Experiment Name: Top-Down Design of VLSI Circuits using Verilog Hardware Description

Language and Electronic Design AutomationAdders and Multiplexers.

Objective:
The objectives of this experiment are:
a.) Learn the basics of behavioral, dataflow, gate and switch level Verilog HDL.
b.) Define digital devices such as adders and multiplexers in behavioral, dataflow and gate level
Verilog HDL, simulate them with ISE Simulator (ISIM) (Xilinx) and synthesize them with XST
8.2 (Xilinx) in ISE WebPack IDE (Xilinx).
c.) Define digital devices such as adders and multiplexers in gate-level and switch level Verilog
HDL, generate physical layout using a silicon compiler Microwind (Microwind), Electric VLSI
Design System, LEdit (Tanner Tools).

2 to 1 MUX:
Circuit Diagram:

Verilog code:
Module
2_to_1MUX(B,A,SEL,Y);
Input A,B,SEL;
Output Y;
Wire SEL_BAR,P,Q;
NOT Inv(SEL_BAR,SEL);
AND AND1(P,A,SEL_BAR);
AND AND2(Q,SEL,B);
OR
Output-Y(Y,P,Q);
endmodule

VERILOG Schematic Diagram:

Output (voltage vs. time):

2 to 2 MUX:

Verilog code:
Module
2_to_1MUX(A0,B0,A1,B1,SEL,Y0,Y1);
Input A0,B0,A1,B1,SEL;
Output Y0,Y1;
Wire SEL_BAR0,P0,Q0,SEL_BAR1,P1,Q1;
NOT Inv0(SEL_BAR0,SEL);
NOT Inv1(SEL_BAR1,SEL);
AND AND_01(P0,A0,SEL_BAR0);
AND AND_02(Q0,SEL,B0);
AND AND_11(P1,A1,SEL_BAR1);
AND AND_12(Q1,SEL,B1);
OR
Output-Y0(Y0,P0,Q0);
OR
Output-Y1(Y1,P1,Q1);
endmodule
VERILOG Schematic Diagram:

Output (voltage vs. time):

Full Adder:

Verilog code:
Module
FULL_adder(A,B,CIN,SUM,CARRY);
Input A,B,CIN;
Output SUM,CARRY;
Wire P,Q,R;
XOR XOR_1(P,A,B);
XOR XOR_2(SUM,P,CIN);
AND AND1(Q,P,CIN);
AND AND2(R,A,B);
OR
CARRY_OUT(CARRY,Q,R);
endmodule

VERILOG Schematic Diagram:

Output (voltage vs. time):

2 bit FULL ADDER:

Verilog code:
Module
2bitFULLadder(A0,B0,A1,B1,SUM_0,SUM_1,Carry_Out);
Input A0,B0,A1,B1;
Output SUM_0,SUM_1,Carry_Out;
Wire P,Q,R,S;
AND AND1(P,A0,B0);
AND AND2(R,P,Q);
AND AND3(S,A1,B1);
XOR XOR_3(Q,A1,B1);
XOR XOR_1(SUM_0,A0,B0);
XOR XOR_2(SUM_1,P,Q);
OR
CARRY_OUT(Carry_Out,R,S);
endmodul

VERILOG Schematic Diagram:

Output (voltage vs. time):

Discussion and Conclusion:


We have done whole experiment by using MICROWIND 3.5. After compiling Verilog file we
got some problem in voltage vs. time graph which was not giving us perfect wave shape.

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