I)iscuss llre fcarurcs ot.\\N4 ;:r:rl Afil.{ clrarl. (RCpv Bhopa!

,:June,2003,
Dri.,3orl_,,
_1. |:.rpl:r irr dirt:r s1,stt-rn dcsig... r,.,.
(RGPY Bhopal, [)ec., 200:
4. llorv will you construct equi'. al ,;'ASM chart
for Mealy and Moore nrachine ? Exptair,
tlris taking with examplcs of Nleal.t ir..' Moore state diagr ant.(RGpV
Bhopul, Jtme; 200,\
2.

5. E.rplain the various blocks of'.a..SiU florvchart.

6. Explain analysis and syrthesis process of AStvl.
7. Write short notes on the follorving

'
''

(RGPY Bhopal, June, 200:

(RGPV Bhopal, June,

200(

(a) Firmware algorithm concept

(O)Algorithmic srate machine.

8. what are some of the advantages and disadvantages ofASM chart

/
9. Ilorv an SM chart can be reatizc by using a MUX and pLA ?

10. Iixplai^ tlre c.'cept of microprogranl*ecl controlrer.

PRO B LEM S
l. Obrain thc ASM clmrt for ftrltorving lirnction

/. = ,.llJ +. ("1)
(rr) It'rvc ca. put rvrrorc cxllrc.ssirl, irr co'clition box.

(l)

If c*ch i'put variablc is ptaccct i. rhc conclition box.

2'. Cttttstrrrct ort.SM blobk thlt has 4 inPut varilblcs (A,

IJ, C, D),3 outlluts (ll: A', ]),
2 cx(
'.tt
patlr.s, lrorthis blockoutput X is alrvays I orrtl
= AD t.CD'arrcl l, = /,1J, .t CD,.

Il

Convcrt thc statc diagrarrr of Fig. 7.g t to ASM chart.

rJL:rt*\._'-

j.

";)

4' Draw the ASM

(o)
Flg.7.B't

.o)

chart to describe a Mealy state machine that detects a sequence

and that asserts a logical I at thc output during the last
state of the seque'nc;.-

L
of
- -'
-- l0l0
:

5' obtain a state diagram for a Moore circuit which produce output I rvhen
it detects the I
sequence I l0l . Overlapping sequOnces arc allowed.
Also consiruct an SM .t
urt fo,
----.'
-"-"'-'
'-' ti,t
"'r._
"':r. jii
givencircuit.
I
I
I

'l
L-I
t
I

Execution of SM block is .............. Vhereas execution of instruction within SM btock is

'l
-.i

4. A path through
5. ASM chart

an

ASM block from entrance to cxit is refcrred to as a

for

contain only one state box.

flATCH THE C()LUTIII

Columnl

i
!

Column tr
Synrbol

ASM chart components

j
l.

-oO'-lI

State box

(A)

2. Decision box

Gf)

rl

I =-

3. Conditionalbox

(q

,.)
rl

,.,

Y
-\

4. ASM block

TRUE/FALSE

l. AnAsM

2
'

chart is a specilication or description of a digital systern

state box is a diamond shapcd box with tnre and falsi branches.

3. Execution of SM block is concunent process.

4. ASM charts are not unique.
5. AsM chart for combinational network contain ouly one state box.

DESCRIPTIVE TYPE QUESTI()IIS

l. What is the fundanrental concept ofhardware./firmware

algorithm ? Explain.
$Cf Y Bhopal, Dec.,2002)

E)(ERCTSES-7
0BJECTIVE TYPE QUESTt0l,tS
l. Thc statc of the system is reprcsr:r.. .a by

box
box

(a) Decision
(c) Condirional

(6) State box

(r/)ASM block.

2. ASM block is a stnrcture consisting

of
(a) State box
(c)

(D) Decision box

conditionarbox

(d) All of the above.

3. Each data systim consists of

(a) Conroller

(D) Data Processor

(d) Both (a) and (b).

(c)ASM

4. ASM charts can described the operation

of

Sequentialcircuit
program

(a)
(c) Soflware

@) conrbinarionarcircuit
(rf Both (a) and (6).

5. A conditional box is shorrr by

(rro

,rrO
(c)

6. []xccutiorr of instnictiorr rvithin SM block

is

j:lj::::::1i:1ryo..'s
(c) Randonr proccss

(0) concuncnr proccss

(rrf notr,

("),;i(6),

7. Basic ctcrrrcnt for branching is

box
block

(a) State
(c) Dccision

(6) Conditional box

(@ASM block.

8. ASM chart for combinational network contain

(o) no stare
(rt;;.
(c) two state box

box

srare box

(rf) number of state box equal

to number of literats.
9. The Moore output are ptaced in the
(a) State box
(6) &nditional box'
(c) Decision box.
(d)ASM block.
microprogrammed conhoiler contror words
fn l
are hetd in
(o) virtuat
il.*ory
(c) Conhol

lo

rrcnx,ry
menr,ry

Fftt H
l.

THE

ErAl{KS

tr'
.l t
lr,.

tL

(6)t;;;i;;

(did;;mory.

are equivatent to a state graph and

ri.
I

t,

L,

.............. is midrvay bctween hardware and

software.

z """"""

F
Ya
0it

it leads directly to a hardware realization.

[r
I

-'l

.l

I,

Yn-t=l thenX< Y.lf Xn-l=Yn-t,tltenitisnot

f = I and Ir-1 =0thenX>l'.lf Xn-, =0and
p,rssible to decide at this stage wheth er X> Y or X < Y or X = L We shill both Xand l/ left by one
t,rr alld compare the bits nroved into ,tn-1 and /r-1. C is a countcr used to count tlte numbcr of
rhi(is in registers Xand l'.

Tt.

ASM chart of circuit is shorvn in Fig. 7.80.

Comparison behveenASM chart and stete diagram

State dia

ASM chart

l)

l'
+r
lo

ASM chart is concented with digital system

which may be combinational or sequential.
ASM charts are more voluminous than state

State diagram is conccrnecl only rvith

sequential system
State diagrams are less volirtlritlous llt:ttt

diagrams
ASM charts may have one or more
cquivalent form.
ASM chart contain'implicit timing
information.
It is often easier to understand the operation
of a digital systcnr by inspection of thc SM

ASM charts.
State diagran$ are unique.
State diagram is not concerned rvith tirne

relationship.
State diagram contain less inforn'ntiort
as compared to n SM cltart.

clurt.
It ttsc nrorc conrpotlctlts tltatt statc diagrattl

It hrs a fcrv cotlll)otlenis.

It is often diftlctrlt ttr tlcsigtt thc rlig,illl
systcm by using statc cli;rgratll its

n SM chlrt is ttlorc stnlctttrctl itt ll0tttrc all(l

lcads dircctly to a lttrclrvarc rcalization.

conrpared to n SM cltart.
Statc diagratl$ are lcss crror prollc.

'l'lrc ASM chart spccifi.* ott thc stcps to bc

codcd ond hclps to prcvcnt ontissions or
crrors.

Conrplrlson bctwocnASM chlrt lnd llorv cltnrt

Flow chnrt

ASM charts are useful in hardwarc

designing of digital systent
ASM chart contain implicit timing
information
ASM chart is a horv chart that defines
hardware algorithm

ASM chart is concerned with digital system

rvhich may be combinational or sequential.

l(' r 8rc

flip'

..xfi0

number

'i

The threg principal cornponents of anASM

chart are state box, decision box and
conditional output box
No such.symbols are used inASM charts.

ed.lf

ASM charts may havc or more equivalent

form.

l. Flow

charts arc usclul is dcsigrrirrg of any

tlpe of systcm.

Flow chart is not conccrned with tinle

relationship.
3. Flow chart describes the sequcnce of
procedural steps and decision paths for
any algorithm..
4. Flow charts provide a clear overview of
the any type of problem and its algoritlurr
Ior solution.
5. It use r.norc components of different sizcs
and shapes than ASM chart.
6. The terminal symbol'in flow chart shorvs
the beginning, end or intemrption point
in a prograrn
7. Flow charts are most probably unique itt
nature.

Thble 7.14

ROl\t address

Nlicroinstruction

Comrnents

R, e-0

Clear R2 counter

R, +- R,, Carry +- 0

Clear carry, set status bits

lf (Z= l) then go to

Done

ifR,

=6

external address
3

R, e-crcR,

Circulate R1 right rvith carry

If

Circulate again ifcrrrry = 6

frz

(carry = 0) then go ro 3

eR, +l,goto9

Ifcarry = l, increment
-

R2.

lixarrrpf e 7.38. Druv'an ASI|I chartfor o nngnirutle contpordtor.

Solulion.

X -Y -C.l,,li -.-

lnpul
lnput
0

C--ll

Ftg.7.80

Two n-bit registers Xand Iare loaded with external inputs. On the start signal Xand.Ir-c

compared.lfx> r'aflip'flopCistobesettot.lfx<Iaflip-hopListobesettol.IfX=lr,a
fl.^,.
flop f is to be set to l. It is assumed that the bic ofXand-lrare respectivel y
Xn_tXn_2...,..Xi,

and In-1 Yn-z,,.,, YtYo.

Initially, clear all flip-flops and thc sequcnce counter C is ser to a nurnber 'a'equal
to numblr
of bits in thc external inputs Xor Y. First MSB of Xond I. namelyXn-1
and yn_1 arcconpared ,t

ffi

11.5.,

Teble 7.13

ROII{ address

Microinstruction

Comnrcnts

<-0;C +- 0

Clear 8-bits registers A and C

B +- (00001010)2

Load input to 8-bit register B

A+

The contents of register A are to be added to the

A+ B

contents of rcgister 8, and the sum transferred

to rcgister

B+B-l

DccrementB

If (B * 0) then go to 2

Add and decrement

C<_A

Done if B = 0. The sunr transferred to register C.

if

B+0

Exanrple 7.37.ll'ritc the mictoprcgramfor the/low chart given in Fig. 7.79for counting
tlrc nuntber of I s in register R 1
Start (Addrcss 8)

Rn-

R2+ l

F19.7.79

Solutlon. The microprogram routine in symbolic form is presented in Table 7.14.

t

be
I

t
I

C.A* 0
B + A{ul:ipticand
Q * Mulriplier
P ._n

tfl[,!n;"oo

C,A*A+ts

Prtx.lucr in

A,()

Fi1.7.77,

l)xanrple 7.35. Dnnv rlte ASlt{ cltortlrtr

XOR gatc,.
Solutlon. Wc knorv that output of
XOR gatc is

Z=A,IJ+AB,
]'hc ASM clrrrt of circuit is shown
bclow

.Exrmpre 736. write the nticrop,*trlli;'ira ,n,

numbersfrom (00000001)2 to
'"-- "'1 swn of an the lirst r0, I oit
IOOOOtOtOlr.
solutlon' The mi^croprogram is symbolic
P* i, given below. The variou.adr.rr* ol
RoM are listed in the nnt cotin'u tn oe
se-cond colunri, the microirutruction
that m,st b" rtir'.,
rt each address is given in symbolic forrn
The comrneni, ir. used
uJls
to
rv
clarify
rrqrrry
-.v
the
tn
register tran rfr
slatenrcnts

ilJ,
!

trl

Ir

:-l

t
i

(Fig' 7'75)'
The state diagram of above ASM chart (Fig. 7 .74) is given below

7=O '

t
I

Z=l
Fi1.7.75
ouputs Tg, Tb
their
label
and
flip-flops
diagram revels the input functions..

Choose four p

?n2

and 13. lnspection of the state

Dru=S'To+ZTt
D7,=STn

D,.

T, +

Z'T'

Dr, =7,
't'lrc logic diagranr is sltown in Fig' 7'76'

s'
7.

T.l

z'
t;
T1
I

a. d its
:

p'

;ined

Ft,9.7.76

A flow chart of the operation

is shown

inFig'7

'77 '

Initial Statc

AC-P*

0
0
n

A <-Alll
(l -- C.'rr

Slilft riglrt CAQ

C--0

lhilld

In state 2n3, register s C, A and Q.r,

inro one conlpositc registe
contents are shifted once to the right to obtain a new partial produit.
The procedure for multiplication using the circuit shown in Fig. 7.73

as'follows:

'ir

CAgani

andlig,7.74is cxptal

'

i'

Trble 7.12

B
Initial value

ll

l0t0

Shift-

First cycle

LJ

l0l0

lll0
0lll
0lll

l0l0

m
m

l0l0

Second cycle

0l0l

001

l0l0

lill

mll

r0l0

0lll

l0l0

mt
tm

lmt
lml

Add
I
shift )
Add
)
shift ,

l0t0

llm

l0l0

Add I
)
sfiift J

Third

r1

ri

cy.l" , ,

Fourth cyclq.

'

e,

ru
| {l

+'L
,lr- t

|ffi

t'i{rl

,!

AR._ Multiplier

BR*
Pp

Muttiplicand

Alt

0's

Pt--Px+ 8n
AR- Ar. - I

t)rrnrple 734, Draw a,t

,n"n[)n'U'li"o

nrultiplier ont! da.rigtr thc conrol logic

ulng one hot approoch, Exploln how lt di/fers from o convantlonal flow chart ?
ASM

(RG PY Bhopal, Dec,, 2007't

Solutlon. ThcASM chart of binary multiplicr is shown in Fig. 7.74. Initially, thc multiplier is
rr Q and the multiplicand is in B. Rcgistcr and corry flip-flop C urc clearcd to zcro tnd thc
rqucnce counter P is set to a binary number 'a'cqual to number of bits in the multiplier. The
(ontrol usc one extcrnal signal ',S' to start the opcrotion. If S - 0, no action occurs and systcm
tmains in an initial state ,S9 when S = l, control goes to state ln1.

Multiplicand

,.t
tr.. -

ron

1;

Flg. 7.73 Block dlagram ol mulUpller c-lrcult.

Present state

Next strte

Qr

Qz

oi

0
0

NIUX

Input conditions

a:

hfl-lX Inputs
NILIX I

MIIX2

,s

00
0l

s'

t0
00

z'
z

z'

None

E'
E

E'

.s

.l
0l

I
I

ffi

't'l

Tl/

rri

s
0

I t,tuxz

733' Draw an ASM chartfof'f l,!i", ,ircuit

.by the- Errmple
that tnurtipries nvo binarynr^brrrl,
repeated addition
melhod.

Fore.g., 4 x 3'= 4 + 4 + 4 = l,2.

t.'l
t-

solutlon' The system consists of,fu".r:.gisters.-r{4,

p4
register 84' the multiplier in register
f^ *.d where multiplicand be in;
Ap and tf,. prooui in'registelpn:il;
conhol *., onr l]
external input to start thr oprr.tioo
*a
o5 rr;t* ;;;t z is the output of a zero detection
's
circuit' Adder circuit adds tbe contents
gf t^,g 4. 'ilr value in z ischecked by the z,,rcf:;
detection circuit
whenz{p becorrs zero after Ji,.n

TheASMchartofcircuitisshown

iifi, irgirt r;p

u'figl.tZ.

is decremented by

l.

il

l.-r
ldntflf,f
".ll
'(

as

.J

-.;an

ir'u
Example 131. Design

the ASM

chartfor JKflip-Iop.

Sotutlon. We know that characteristic equation of JK flip-flop

ching

is

Q(+l)= tOfO+RQ0

i,

The ASM chart of JK flip-flop is shown belorv.

I

l
I

,J
,l
I

l
:l
I

Q(ttl) -

F19.7.69

Ilxnrnplc 7,32. A systcn contisting of two ragistars R 1

ancl R2 nui n fiip'llop E counts the rumbcr ol I I loaded
inro R 1 ancl sets R2 that nuntben Draw the ASI'r chart for
the syitents and design the control circuit MUX'
(RG PY BhoPal, Dec,, 2007)

Solutlon. The systcm consists of two registers R1 and

R2 and a flip-flop E. The control uses one external input 'lto
slart the operation and two stitus input 6 and Z. E is the
output of the flip-flop andZ is the output of a circuitlhat
chccks contents of register

R 1 for

R1*lnput
Rr- Alll's
Rr<- Rt+l

all 0's. Esbh bit from register

R1 is shifted one at a time to flip-flop 6. Tbe value in E is

checked by the conEol, apd each time it is equal to l, register

R2 is incremented bY

l.

TheASM chart of circuit is shown in Fig. 7.70.

F19.7.70

Norv rve considcr that cnrcrgency vehicle is coming. I{ere we willglow red for NS as r*,eli
s
for EW rvltcn enlergency vehiclc is present. Secondly, rve rvill allorv output )', so that u,e
;r
<
provide atrdio sound, so that other witl come to know about entergency vehiite. At each
switching
rve n'ill check per emergency signal (8"). Therefore, ASM chart will
be

Rcd

Red

EW
N.S

EW
NS

Crccn

Yellow

t:

L.
ft
t,

{t

F19.7.68

:
i

I
r_

t-l
I
,i

l)uring the data system designing, designcr should consider the fiollowing points.

l.

Cost: depending on the nature of the systerq the designer must sclect the most economical
solution for the givcn systenl

L Efficiency

re

Data system should be eflicient, having low propagation delay

i. e.

fast response

tirne.

()..

3. System should be reliable and must have some securiry measure to protect the sensitive
data in protected location.

,l

4. The structure (hardware configuration)

l1
'ts

,l

is modular, regular and independent of the particular

computation.
The block diagram is shou'n in Fig. 7.67 which indicates that horv a digital system control
tlrc physical systeft.

in

F19.7.67.

Exanrplc 7,30. Devalop ASM chartlor trottrc signal controller ut thc intt'r:;eclion. The
bc ONfor 30.tcc arul yellox, light should be ON for l0 scc. l'laka
ltnvislon for oil cntugancy vahiclc lo pass through hy stopping truttrc d rcquirad,
(RGPV Bhopul, Junc, 2006)

y*'n/rcd lights shoulds

tlrv
hq

s;'

Solutlon. First wc will tske scqucncc of traffic. Wq won't considcr cmcrgcncy condition.
thcreforc our tralTic signolling schemc is os follows :
1
- ReC
' I 30t..
NS - GreenJ

(a) EW

tat
llcr

(D)

sw -.Red

(c)

rw - Yellowl

)I 5
,psi

n8

J)sec

- Greenl ru
^^ sec
NS - Red J

ihe

e''tl
si-

-Red

(.ft gw

)tt'
NS -y.llo*J

NS

nor

:1

g.

ith"L

ri ls

'

(e)

rw - Yellowl

NS-Red J)sec

(rEw-Red

l )tt'
-

NS -Yruo*J

Now, continue from(o)

l.

In nricroprogramming approach the overallspeed of the system is lou,.

2. Ir{icroprograttrnilng provides a rvcll strucfured control organization.

3. It

is more expensive than hardwired

(fixed network).

4. With nticroprogramming nuny additions and changes are rnade by simply changing the
nucroprogram in the control tlremory. A small change in the hardwired (fixed nefwork)
approach may lead to redesigning the entire system.

5. Microprogram control organization is more efficient in large, complicated systems.

7.8.-

DATA SYSTEM DESIGNING

Data systenr processes the data and produce the required output. Each dara systenl consists
of controller and data processor.

The relationship between control and the data processor i1 a data systenl is shorvn in

Fig.1.66.

lnputs

l:rtcln.rl
lnputs

l);ttit l'roc'csstlt

--

.Stiltu$ l0 for0litt ion

Outputs

controltcr is a sPccial scqucntial .,r.,1',0;t1;l6r..riu., input fronr coch coprponcnts of t6c

systctll lttd outcr irttcrfacc ond gcncratc thc control signals thlt control thc opcration to bc
pcrftrrntccl by thc data proccssor. Tltc data proccisor part may bc o gcncral-pfirposc proccssor
unit' or it rrray consist of individual rcgistcrs ond associoted digital functions.
Design of a digital system can be dividcd into two categories, first part is design the data
processor which stores the data in the flip-flops or register and second part is design a controller
which control the corrcct operation of sequence to be performed Uy ttre data processor.
Before designing the data systerq designer should know very well, what the system works
and what is the need for sptern In general design a data system involves the following steps.

l.
Z

'

:''
!,
t
i

*,

It

Given the word description of the requirement obtain an algorithm necessary for solving a
design problern Algorithm may be in the form of flow chart, ASM chart, state diagr"- ot
table. orHDL.

!,j
!,.
L'I

From the algorithm determine the various components required for designing, such as the
size and number of flipflops needed to store the inf6rmation and the kind of operational
unit such as adder conparaton etc., which af necessary to perform the required processing:.

{t
-l

3. Generate the timing diagnm which will conbol the sequence of different steps ofatgorithm
A timing diagram clarifies the timing sequence and other relationships among thelarious
control signals in the subsystern

4. Synthesize the controller

to generate the timing signats.

5. Test the system with appropriate test signals.

t
tl
t!

1"',
I

t$
rN

i :'

&in?'
?

.t

rTI lll

"t

'

I\{icroprogrammed controller. In a microprogrammed controller, control words are

lcld in a separate memory callcd the control memory. Each control rvord contains signals to
uctivate one or more miciooperations when these words are rctrieved in a sequence a set of
rrricroperations are activated that will complcte the desired task. The set of microoperations
lrrricroinstructions) for the control of a computation sequence is called microprogram.
Structure of a microgrammed controller. The structure of a typical morden

7.7,6.

rrricroprogrammed control unit is shown in Eig.7.65.

i
I

nr,.rnol
conrrol

f
[_
Control
lrurtclirln

lricltl
Contrtll .Sign:rls
Flg. 7.65 A mlcroprogrammod controllor'

MBI{ of
ClvlBR (Control Menory Bttllcr Ragtsitri,'t'tt CMllR functions tltc sntttc as thc
rctricvcd fronr
rhc main mcnpry. It is bosicsttya taictr, on.l o.t os I buffcr for thc nticroitrstructiotts
thc control rncmory. Each microinstnrction will hovc thrcc distinct ficlds
Conditiorr selects
Branch address field
Control function field.
The condition select

'l
I

t:
l'

fie ld selects the

external condition to be tested. If it is true, the output

input of the
of the multiplexer will be l. The output of the MUx is connected to the load / Inc
active and
microprogramcounter (MpC). If the output of the MUX is true, then load input will be
field of the
rhe MpC will be loaded with the uidrrs specilied in the branch address
will be active and
microinstruction. If the output of the MUX is false, then increment input t t"t I
field gives the
the MpC will point to thc next microinstnrction to be executed. Aconhol function
values of the conhol signals.
the
MpC (Mtcruprogrsm Counter).. The tlpical functio'n ofthe MPC include incrementing
a computed
current address by one, transmitting .n r*ir-ally specified address, generating
'branch ad&ess, or speciffing an initial address.

according
Exlernal condirlon select MIJX.. This MUX selects one ofttre external conditiors
to the contents of the condition select ficld of the microirutruction'
The conparison of a microprogramnrd controller with respect to a controller implemcnted
as a

lixed network are as follows

Exampfc 7.29. Design the ci,rtuol hgic c{Fig. 7.61 using pLA.
Solution. 'l'lrc statc lahlc corl(..3rr,:rrling to thc ASM chart

lhblc

of Fig. 7.61 is shown.ri

7. 10.

Table.7.l0
Prescnt State

Ncxt State

Qr Qz

Q*rQ'z

00
00
0l
0l

00
0l
l0
ll
00
lt
t0
00
t0
rl

ll
ll

lt
t0
l0
l0

Inputs

Outputs

xy
0x
lx

To

Tt T2

T3

1000
1000
0100
0t00
0001
0001
0001
0010
00t0
0010

xQ
xl
0x
lt
l0
0x
l0
tl

'l'he I'l.A progranl rablc

is strorvn in'lirblc Z. I | .

l'lblc 7.1I
I'rotluct lcrnr

I
2
3

4
5

6
7
8

l0

. Input.r
l2
34
.f,'
h Qz t'
000
0 0 l0 I -0
0 I -l
ll0
l I lt
I I l0
I 0 0l0
l0
l0
ll

Ou(puts

123456

Qf Qf ro

l-tlll-

ll

r r

The block diagramof PLA conhol is shown in Fig. 7.64.

3'

.l
2

PT.A

46
F19.7.64

t-

l-

l-l-

2l

r'2 r'r

tll
l-

r't

I -l

,l

tt
rl

pnEnffii
-.1.--

to the next state and outputs in the state table. The numbcr of states detennines the number
flip-flops for the sequence register.

tl

of

The following example demonstrates the procedure for designing the conrrol logic rvith

PLA.

Exanrple 7.28. Derive the PLA program table

Table.7.8.

-)To
lr,
I

rl-

-,T.,
il
-, _;r3
I

the control x,hose st.tte tdble is gi .,en in

Table.7.8
;
!

Present State

Nert State

Qr Qz

hQz

I
-l

for

I
,I

Inputs

Outputs

.ryz

00

00

0xx

ToTtT2
1000

00

0l

lxx

1000

0l

tt

xlx

0100

0l

0t

x0x

0100

ll

00

ll

0l

xxl

l
I

I
I

I
,
It
I

It

,le fronr

h I)[.A

0.

00

t0

itrons.

00 r

Solutlort. 'l'hc I'LA progrsnl tablc can bc obtaincd dircctly frorrr the statc tlblc witout thc
nccd for sirnplilication proccdurcs. Thc PLAprogrom tablc is givcn iq'l'ablc 7.9.

Trblc 7.9
Product
ternr

Outnuts

Innuts

QrQzx

(.

00

, inputs

00

rt .fthe

'om the
te tabte
itrcs no
tinus to

0l

l-

0l

ll

n't

ll

,1i

lftfi

, ^lor-

carc

n rdto
'L.rt are
ui'alent

t23456
QrQzToTlT2z
I
I
I

I
I

lI
I

2l

NIUX

srI

0
I

2
3

Ft1.7,62

's

.tlrcASM uslng P!4. 'l'hc dcsign ofa I'}LA control rcquircs tlat rvc obtain rhc storc tablc fror:
chart of thc circuit.'Ihc biock diagramofrhc pl.l\controlis
shown i1l;ig. 7.63.^I-heF t
nlcthod is supcrior to o RoM if ttrc statc tablc contoins largc
nunrbcr of don,t carc conclitioru.
7

'7

Oulput$

Flg.7.6s.
The state table gives essentially all the information rcqufued
for obtaining the pLA prog{,:m
table' The PLA progftlm table is a list ofproduct terms, one for
each row in the state table, infur
and their corresponding outputs. For eacch product
tenq the inputs are marked with l. 0 q-,(dash)' A I in the input colurnn specifies u p.tt
from the corresponding

inputioilffil;lj;

AND gate that forms the'product term. A 0 in the input column specifies
a path from thc
c-oresponding complement input to the input of the nNO gate.
The ,X,s in the state ta' lc
.'designate
don't-care conditions and inpry no connection for the pLA.
A .-'(;;;J

ililU

conne-ction in the program table. The 0's in the output

columrs also indicatc no connections to
the OR gates within the

PL,A.

""1','

The conversion of the state table to a PLA program table is ycry

e8sy. The don't clic
conditioru in the input columrs and the 0's in the nextitate and
output colu,urs are change<, ;o
'-' (dash) i.e. no connection and all other entries remain the sanrc. rhr input
cquivalent to the prescnt state and inputs in the state table. The outputs
ortm pu are equiva[enr

to;;'ifiir;

I
t

c .tft

tr

1
.l

_Ir.
,-){-

'o

-Tr
- l-T'
-T1

Flg.7.6l
7.61 shorvs att
Thc cquivalcnt ASM chart of Fig .7 ,60 hai four blocks-onc for coch statc. Fig.
SM chart for tltc statc diagrum of Fig. 7.60.

Trble 7.7

i
I
I

't Jz)

.:

Prcscnt State

Next Statc

hQt
00
00
0l
0l

Qr Qz

ll
ll
ll

l0
l0
l0

00
0l
ll
l0
00
ll
l0
00
l0
ll

Input C6ndltlons

MUX lnputs

Mtxl

MT.D(2

ry * xy'
=x

xy

xy'

ry'+ry

x)'

xy

=x

x'
x

v'
x'
ry
xy'

x'

I.r)gr( diagramofconEol unit is shown in Fig.7.62

The MUX inputs from the table are used in the conhol imptementation of

Fi

g.7 .59.

0
I

MUX

',
3

sr-

so

0
I

MUX2

Ftg.7.S9
If xnrrrplc

7,27, I'hc state liagrum o/ a contrcl unit is slrcrr,tt belox,.

x.0
00

xt

t=l
I=l

aQ

,A-

x=l
I=0

Ftg.7.60

(a) Draw the equlvalent ASM chart, leaving the state boxes empty.
(b) Design the control using nultiplexers,
(RGPI, Bhopal, June, 2007)Solution. (a)

,l

,'|

1:Effi'
rnntr0l
I

.l

peption
I

,t

,
I

F19.7.58

Solutlon. Tablc 7.6 gives the infornration for 0reASM

'isa

'gister.

chart ofFig. 7.58. The input conditioru

listed in the table arc obtained from the decision boxcs in the ASM chart. Thc
two colunur undcr
MUX inputs in the table specify the input logic that must be applied to MUX. The MUX
input fo,
cach present state is dctermined from the input conditions *tln the next
state of the flip-flop is
equal to l.

'r '' has

: .rlly)
of the
'r iion
It ,!the
L.Y,

Present State

Qr

Qz

00
00
00
0l
0l
0l
l0
l0
ll
ll

Next Stete

Trble7.6
Input Conditlons

Qr Qz

l0
0'l
ll
l0
0l
ll

t0
00

tl
00

x
x.'

y'

MUX Inputs

Mtxl
,+x'!

*x* y

MTIX2

x'Y * x'Y'

x'

--

x'v
x

x * x'y'

x'y

-x*'l'

x'y'
r''

x'Y * x'Y'

=r'

x'

x'
x

t
Example 7 '25' The state diagran, of a control unir is
b),the oneflip-flop per state nrethod.

shorvtr

in 'Fig.
'6' 7.56.
"-"' Design

tlte contrri

,Z=0

sotution. choose five Dflip-flops."iilot itneir outputs To,Tt,72,

-- - u' ' r z" T3and
of the state diagram reveats the input hrnctions. '
" r ?"a. Inspecrion

h=0

D7t

To + z'

Drz =

Tt

Tz

D7r=zT2

Dt't

Tl +

Ta '

1'he logic diagranr is shown in Fig. 7.57.

F19.7.57

tn

il;;'

sares are reptaced by muttiptexer. rt is

l"l:1.r-.u*rJiilti:lers. $r.:g:9_l-"qi.
ts or MUX ;;i
t
H: :t-1t-"11
::::',',:level
:ff:contairu
3:,T1a.register
! ::l ^' " rthat hold the pt.r.niuinary ;'; ;:; J#"'ffi
j

"dlla,\
*.rrv intro
lrtla\r rgvgl
,:;:il::
*:ffi liiffi:1?'i:::l*::""*"l*Trif-T:":,tTt:-:i"_'ry:F-i[-n;;;;;;ili,
ffi il:i:i::T"_1fjj'^linputsandarsotlrheserectioiri",;;?;;;ffi i:ffi ;#il"iu{l
iny uts
nn* re termine iffi ;,i, ffi ff
11H ;t;T::Hl'"l"" givin
f IrIl
;1n:1s The
f
in'thosM
chart. in order to crarify,r,, pror.i*"'.;fffi:.,'ili
L:Xffjrr:,t:gg:ru
fo
lo wing design exanples.
is

*t

srate value.

11e-

de

Errmple 7.26. Design the control whose ASM chort is given

in Fig. 7.5g using
rcglste4
and decoden

il

MC2X,

,l
6l
I
I
I
I

-t
:l
i
I

1i

9'EFtii
- !_;

rii .,iri*r,.. i

' ..

Dro=x'7'6-77

Df,

T(l

Dr'- = Tr

^'z =), :I2

u7,
Dfo = Tt
Drr, : )rr2

l:

l:,
a

Di =Ts
D; = Tt+ Tr,'
The logic didgrarn is shorvn in Fig. 7.55.

lr

ii

It

-!

t,

'a

I
I

''q

'l
li

I
1

I
I
I

j.!

control
gular

,inbc
re necd

.l

munl

srln of

stale
'I

'I

.-J
'I
\

n..nd

is

tc

AND

ntot

'arr1 wc

clcar clk
F19.7.55

7'33

m
QrQo

QrQo

000t il

t0

000t

il

t0

Dr = x'Qr'Qo

Do=x+Qr'Qo
Ft,1.7.52

The input filnctions to the D flip-flops can also be expressed as follorvs

D1 : x'71

Dg= x
rvhere

To: Qt' Qo', Tl: Ql

Q6 and

T1.

Tz: Qt Qz

The logic diagram of the conrrol unit is shorvn in Fig. 7.53.

F19.7.53

3.

Uslng onc fllp-flop per strtc. iiiir #ilt"d uscs one flip-flop per stare in rhc contrft I
scquential circuit. Eoch flip-flop represcnts o statc ond only one flip-flop is sct at any particul;
i
time, white all others are clearcd. The advantage of this method is sirnplicity with which it can t :
.
designed. The control unit logic can be derived directly from thc state diagram without the need l
of state or cxcitation tables. The rnain disadvantage of this method is 0rat it uses a maximu ,
.nurnber of flip-flops. Considet some specific examples that demonstrate the detailed design 0.li
conbol'units by this
I
7.7

method.

Example 7,24. A control unit has two inputs x ary! y and eight states. TIte controf rro;:ij
diagram is shown in Fig. 7.54. Design the control using eight

*=9r-

Y=

Dltip-flops.

n"i

il
I

F19.7.54

Solutlon. Thc condition for setting a givcn flip-flop

is specified in the state diagram and . i

obtained from the conditionspecified in the directed lines going into a given flip-flopstateAND'!
(logical and) with the previots flip-flop state. Iftbere arc more than one directed tine going
into ,'l
state, all conditions must be logicat Oifed. Using this procedure for the giveri st.i. Ai.t
obtain the input functions.

i*';,'

ltr.l
rI

,lrl

rffi

l-l:lrl

To =

Qo'

Tl=Q:

To = Qr'Qo

Fig.7.50
The logic diagram of the control is shown in Fig. 7.51

F19.7.51

7,7,2,

Uslng D fllp-flops snd dccodcr. Thc nuin advontage of this nrcthod is that wc con
drrcctly obtain thc input functions from the statc tablc without the nccd of an cxcitation tablc.
'llris is bccsusc thc next state is the samc as thc input rcquirement for thc D flip-flops. Then,
tnstead of using the flip-flop outputs as the present state condition, we nright as wcll usc the
output of the decoder to supply this information, for that insert a decoder at the output of thc flipflops to obtain the necessary outputs. Now realize the conhol unit using gates, flip-Ilops and decoder.

Examplc 7,23, Design lhe contrcl unit whose state table is given in Table 7.3 using logic
g,iltcs, Dflip-flops and decoder.
Solution.
Teble.7.5
Present State

Syntol

Prcsent
State

hQo
To
To
T1
T1

T2
T2

00
00
0l
0l
ll
ll

Input

Flip-tlops
. Inputs

Next
Statc

Qr

Output

'

Qo

D1 Do

To

TtT2z
000
0 00
100
100

I
o

I
I

0r0

0ll

The srate tabre corresponding

to rhe AsM chart (Fig.

trtl

,, shown in Tabre 7.3.

Tablc. T-3

Present

Present
State

State
Synrbot

Input

hQo

Next
State

.r

Qt

Output

ToTtT2

Qo

00
0l
tt
0l
00
0t
lablc. 7 4 shorv lhc. excitatiorr
rable ol.rhc nitnolrm

t000
1000
0100
0 I 0'0
00t0
00tl

li iI

'Iirbte 7.4

I'rcsenl Stnte

0.0
00

0
I

0l
l.
tl

0
I

000t il

t0

0'

4 Kr Jo Ko
oxox
oxtx

0
I

lxxO
0X;0
xlxt
xlx0

00 0t tt

t0

Jt = r'Qo

Kt=l

00 0t lt

t0

Joo'
simitarty, the ttuee sinplified
outpur 0x1,1;1i
To- Qo'
Tt - Qt' Qo

*,

000t

il

t0

It = r'Qr

9r%

Tz'Qt

Flipfloplnpurs

00
0t
It
0t
00
0l

0t

Ncrt Strte

Uslng JK flip-flops. The following procedure can bc used for connoller dcsi

:d.i,e.

7.7,1.

rhm

using JK flip-flops

The first step is to assign binary values to each state in lhe ASM chart.
a list of prescnt slnlcr.
2. .Obtain the state table for a controller. A state table for a controller is
llrc
inputs, their corresponding next states and ouputs. The inputs are taken frttttt
to tlr
conditions in the decision boxes of the ASM chart. The ouputs are equivalcnt

l.

'rt $e
l"ons
3en

r uits

present state of the connol.

3. Obtain the excitation table of the flip-flop inputs'
4. Find a simplified expression for ouput and the flip-flop inputs'

)utl'ef
3c,th

rl

' iy

5. Realize the control unit using gates and flip-flops'

ln order the clarify the procedure, consider the following example.
detcctttr tlrttt
Exarnple 7,22. Drav,an ASI{ cltart ancl state diagram to describe a sequence
detects a seqye,rce of " l0l ". Design the control unit using JK flip-tlop'

r'.rry,
r. -:

of

dware

Solution. Figure 7.47 gives the corresponding

not
ls not
l^vc a
v l,cr,

0r

'l'o

t) ..
ttv

t/0
(\z----

vl

f* \

T1

-*_-1.|r
\

state diagram for a given seqtlence dctce tor'

(Y()

\i./

ttcd

l,-kccl

o/()
I

: rory I
I

torrgcr

'

F19.7.47

l:ig. 7.48 givcs thc corrcsponding ASM chart for

I givcn scquctlcc dctcctor'

QrQo'0

QrQo= 0t

rt

of
;1 tern
ts

letailed

F19.7.48

QlQs=

ll

t'

Gencrally an algorithm rvill contain a number of procedural stcps which are rcsult-oriented
i.e.
depcndcnt on results of prcvious steps. A convenilnt method foi presenting
hardware atgorithr
is a flow chart. Flow charts are uscful in the hardware design oidigital
slystem. It convert the
given word information to an information diagram that enumerates
ih.. r.qu.nce of operationtogether rvith the conditions necessary for their execulion. A special
flow chart that has beer
developed specifically to define hardware algorithm is cailed an
ASM chart.
Firntrvare algoritlinr. Firmware consists of programs that are included in
digital circuit ,
during their manufacture. Firmware is used u'hen ttre programs
must be retained in case of pog,e. \
failure and rvhen programs are not expected ro ue ctrariged. The
microprogram facilitates thg
irnplementation of hardlare and is therefore, called firmware to
distinguistr i-t from software.
A microprogrammed computer has its centralprocessing unit intplemented primarily
by a
RoM rather than by discrete logic. Each nrenrory location in tlris Rolv{, c:rllecl
a control nremorl
holds a nricroinslrttctiott, the torvest leve[ instruction a conrpqtcr
can exe,:r(c. A sequence o
ttticroinstructions is knot',rt as a nricroprogranr or finnrvare.
A firnlvare is rpitlg,ay btt*,een hardrvare
attd softrvare' Wc'cart cottsider nticroprogranrnring as softn'arc
lha-t cap irrrpler'c.'t frrnctio's no
prescttt in thc hardrvarc. Microprogran$ can be ctranged
in trvo \\,ays. ll'rlrc ct'rptrolrrrcnrory is no,
RoM. tltc ttscr catt rvrilc il llelv scqucncc of nricroiristnrctions inro it. 'l'lrc
c.rrrputcr.ury lravc a
progl'atll tlt:tt catt altcr thc ttticroprograttt stureil in thc conrrol
nrclrory. llsu:rlly,5or'cver
ttticr.Pr.gra.Ls ilrc clrl'gctl by clrnngi'g thc co'trol r'crrxrry.
Itt a ltorizotttllltticrtlittstruclion (l:ig.7.46), cach controtsigrral
witlirr r6c CI,U is rcprcsc.tcr'
b;,' nttt ltit in thc cotltrol lickl, In attotltcir lbrnr
of nricroprogranrnring, callcct vcrtical or plckc<rrricroprograttttttittg scvct'al cotttrol sign:rls arc cncodcct into
a srrurllcr
of bits.
vcrtical ttticroitlstntction tlttts ltas thc aclvarrtflgc of dccrcasing 'urrrbcr
thc sizc of co'trol nlcnlor)
j]lllf:L:'111.9:::1':rpl"ving cliso<lvarrtagc of-rlccrcascc ncxiuility, sincc it is no longci
possiblc to havc irrdividual
to cach corrtrol point.
'cccss

Nlicroinst ruct ion address

Jump Condition
Systenr Bus Control Signals
Internal CPU Conrrol Signals

(a) Hodzontal Microlnslructlon

(b) Verllcal Mlcrolnstruction

T,T.

coNTRoLtER

DE'TGN

Fis'7'46
''-

system controlter is a^spccial sequential circuit

that receives input frorn each component, or j
thc system and outer interface and ginerate the control
signats that control the whole systern
The subsequent sectiors of this chapier deal with
rp..inr r*amplc ..-r
tbat ewr'rt'':rucls
demonstrate tbe
lrrq sgratle11
detailed 'dcsign of conuol unit.
,

tt

,!

,el

:j

tt. ')

Solutlon.

hd

,:

)"

--l
I
I

l:

t:
i:
-;--J

--l

t.

Up-down

counlcr

Ft,g.7.45

In thc Fig.7.45,

Count r nunlbcr of pcoplc in o room

ifx-lnoentry
if y

0 peoplc entcr the room

I no onc

leave the room

= 0 people leave the room

M = Mode select
M :0 fer up counter.
M = I for down counter.
1,6.

HARDWARE AND FIRIAWARE ALGORITHNilS

The most challenging and creative part ofthe design ii the establishment of design objectives
rnd the formulation of algorithms and procedures for achieving the given objectives. This task
(rnnot be automated and require the mental reasoning of a lluman designer. Dcsigner cannot

&vclop algorithm without.

r, r
:nul

:hn
ntl
fan

.1.

Thoroughly understanding the problem

Assuming initial conliguration of equipmont for implementing the procedure.

Tbe algori0rm is stated by a finite nunber ofwclldefined procedural steps. Thts an algorithm
n o procedtue that specifies a finite sct of steps which if followed give the solution to a problern

Hrrdwrre rlgorlthnu Hardware algorithms arc used to specify thc control sequence and
.hta processing tasls of a digital systern A hardware qlgorithm is a finite number of wclldefined
pocedural steps that specifies how to inplenrnt a problem with a given piece of equipnrnt.

Exanrple 7.20. Draw the ASM chart of a 2 bit up-tlown couttter *,ith
eilcrnal reser inpur.
Solution. when up is high, count sequence is up i.e. 0 - I -2-3-0..... and when up
is low, the
countcr $'ill count-down" i.e.3 '2 ' | ' 0 - 3..... . As the counter must
reset back to initial state .,00,,
when external reset input is high.

Erampfe 7,21, c'onstntct an ASM yTi;'if

,)src^ that counts rhe number of
people in a room' People enler the roomfrom one ".digital
dooi with a photocell that changes a signal
x from I to 0 when the tight is interruited.
They leave the room from a second door with
a
similar photocell with a signal y: Eoth x and y are synchrcn4ed
with the clock, but thq may
stay on or ofifor more lhan one clock'pulse piriod. Tie
data-processorsubsystem consists ofon
up-down counter with a display of lls contents.

l
-t
.t

Lint 3',,

o
l.in[.5

Att-to

t
i

F19.7.43

Tlrc next statc and output equations using thc state sssignmcnt
Ss,AB -001 SyAB -01;.12,
Output

Z = 18"N,
linl

The next statc

A+

1.t

AB-ll;Sj,AB - l0;arcgivenby

ofl

(,,{+) is

=Vgx+M+@
a linl I
2
lin&

lanl

= ZBX + ABX + ABX + ABX

= BX(Z+ 4+ ABV + N)
BX+ AB
The next state of I (B+) is
=

n* = 7Ex + AEx +7ax + ABX

linl 2
linl I
linl I
lint t
= Ex(Z+ O+ BX(Z+ A)

=X(B+B)
: )(,

(ldernpotent law)

Norv to form SM chart from abovc state diagranr, for each states draw state boxcs. Now afier
each state boxes put the inputX in decisi,,n box. Put the output in conditionalbox in patl where
it will I and connect next state links. Fig. l.';J .''rorvs an SM chart for the state diagram given in
Fig.7.39.

The next-state and output equations using the state assignment

So,

AB = 00; 51, AB = 0t;52,

Ouput Z :

AB: I l; are given by following equations

BX (from link 4)

The next state of 8 (B+) is

r>+

= ABX+ABX+ABX
link I
lin! 2
lin! 3
= |EX + /gX + \AX + ABF (lndc.mpotent

larv)

= 786+B)+ oXG+ el

=17+B)X
'l'hc ncxt sratc

ofl

(ul+) is

+ ARX = IIX
'+ 47oX
linl I
linl l
I;ig. 7.41 shows tlrc rcalization of SM clrarr.

ct(rcx
clock

F19.7.41

7.19. Draw the ASM chart of a sequence detector to detect the input sequencQ
.. . . ^ Ptltple
" I 10". Derive the next state and output equations by tracing link poths on
the ASM tiort.
I

Solutlon.

t
I
t
I

F/ig.7.42

F
ilE;

-.i,,1'1
Ncxt, rvc will realize the SM chart using D flip-flops and logic gates.

r state

i'rill
t

_l

clock

Fig.7.38

Exanrple 7.18. A sequenrial cirruit has one input and one olttlrut, giles oulPut I wltttt il
r(,ceir.es input I followittg u .sting d tt'o or lltree const'culit'e irynl 0. I)tuv' ttntl rculi:t' tltc Sll
churt usittg Dflip-flo1ts ttnd logic gatas.
Solutiott.
0/(l

.S,,

|/0
f'l
,l

vl

rj

F19.7.39

Link

I
I

.1

:l

_t

Link 2

9i

I
I
I

I
I

s2
I
I
I

Link

4:

Flg.7.40

v0

Fig.7.36

Now to form SM chart front Fig. 7.36, foieach shtes drarv state
boxes. Nowafter each star
boxes put the inputxin decision box. Put thc ouput in
conditional output
r -- box
---- in path where it r,,i;
I and connect next state links.

! Alt=g1

,l..

t,

output

z=ABX(fromtink5)

The next state

ofl

(l+)

l'

Fts'7'37'

:
t

is

A' = TLx6omtink t) + ABV(from fir* +l

Similarly the next

srate

ofg (B+) is

+ 4aj + 4px + laX

a+ = lt4x
linl2 linlt

ti*t

= ZEx +

1ax

fnit

+ ZaX + ABX

= 7x(E + q+ BX(Z+ A)

=7x+BX

.l

'I

-)

v,wr ffi
fiqput

'l 'lnce
:
I

t'

t;
).
)
i

It
,l
;

I glven

(,i

pul

| (Fig

Flg.7.Qs

Exanrple 7.17, A sequential circuit hasine'input x

nuntbcr of t in the input is divisible by 3.

'

aircl one

oulprtt z. Outpttt z

(a) Draw the equivolent state diagrant

(b) Convert the state diagram to SM charts'

(c) Realize the sM chart using a D tlip-flop aud logic gates.

I,

i/'total

Exemple 7.16. A sequence recognizer has h+'o inputs (x and y) andone output (z). If input
sequetrce of pairs xy = 11,00,10 the output v'ill be l. Draw the AStl chart of a sequence
recognizer.

'

Solution.

Fig.7.33
We rvill solvc thir problenr by first constructing a statc diagranr 'l'he statc diagranr for giver.
sequence recognizcr is shorur in Fig. 7.33.

Norv to forruASA{ clr:rrt for cach statcs draw onc statc box. Norv alicr clch stiltc boxcs pu
thc inputs in dccision box. I)ut thc output in conditional output box in paths rvhcrc it will I (Fig
7.34). Conncct thc neet statc by link by inspccting statc diajrant as sltowrr in l;ig. 7.34..

F19.7.34

The conpleteASM chart is shown in Fig. 7.35.

f-

-:,
t

tl

,.|
y'os

ph
I

Flg. 7.32 (b).

scquence
ttce of pairs xy =

-r' -- YrY"e"ec 'sel

01,0t,tt.00.
0l,0t.tt.
00

.::';fi:;-T..:'::::::."i::rl!,

the state diagram for a sequence

rccognizer.

(RGPV Dltopal, Jurte

2004
by nrst consrucrine a sratc diagranr
Fig. 7.31 gives

Now lo fornr sM chart' for

caclt statcs
srate bo.xcs,
our'ut i^ rrrc srarc rr..x. r)ur
bo'r aticr caclt statc bo.x an.l
conncct trrc
statc'rrr
ti'k by inspcctirg srarc. graprr
'c.rt
tro't rbrst:rrc^ i,;i;,"n
in rrig ?3;i;;'\rrccor'prcr..tsr,,,

;:tJil.

i'put i'ttccisitlrt

ffl1lil'i;,i;,i.-ij i:!;l;itr'a

r-\(}
\Ys

--r
I

t-

--"1:{;.

I.
t.

L-

:'
I

L,
(

I
I

D-;7

t1l+

,\,

7.32 (a).

1o,/

t/o
;,

il

,r5
6

,.q

tate

'm

.,1 wl1
Solution.

.t

'I

lr

Ir
I

a-

F19.7.29

The state diagram for given system is shown in Fig' 7'29'

S,.'

t7
tl

F19.7.30

the output in statc box' Put

NowtoformsMchart,forcachstatedrawstateboxsndput link by insPccting thc

next state
after each stttc box and connect the

input in decision box

Ji"gra* The ASM chrrt is showu in Fig' 7'30'

state

Table 7.1 shows the transition table for Fig. 7 .26. Table 7.2 gives the corresponding state
table for Tablc 7.1. Wc have madc the state assignment Q = 0 for S9 and Q = I for 51.
Teble 7.2

Present state

Nert state (Q+), S

X1Y1=00

0l

l0

ll

so

So, o

So, I

So,l

.11, 0

.Sl

sg, I

51, o

51, o

St,

a sequential machine is shown

nFig.7 .27.

A state graph for

I t/0

lt/t

00/0

0t/l

t0/l

tu0

l/0

00/t
F19.7.27

To drive SM chart frorn Mcaly state diagranr, fornt 2 statc boxcs for cach statc 56 and 51.
Aflcr caclt state box put input in dccision box and put corrditiorral output box in thc path wherc
Mcaly outputs arc l. Fig. 7.28 givcs thc corrcspondirrg SM chart for a givcn circuir.

r
I
I

t'
..

t
(
I

I
I
I

F19.7.28

'',,wsynchronoussequentials7stemhg'tnoinputsXandYandoneoutputZ'',
wh.en
the sumfr the inputs b a nultiple of 3. the outpuit ls tnte, otherwise

A{M chart that describet

it

the above machine.

is

false.

Driw th\,

t,l
'-.t

_Ll

l( .tYfl

.i..

"

.Ss:Initialstate
ifS= I then
Rtelnput,{

-rd''.

Ra

Input 8.

Go to 51.

rvhere, external input S is uscd to start the operation.

if

S = 0 then go to S9.

.S1 : R,a

Rl+ (2's complemcnt ofRg)

Borrow +- Conplemcnt of carry,

Go to 52.

52 : If (Bonow = 0) then go to Ss

I
I

If(Bonow: l) then

'
I

Rl

Go to
-.rut

)t)

(2's conplement of

R,a

Sg.

Exarnple 1.13. A sequcntial circuit has oneflip-tlop Q ; ttt'o ittltut x, und y; and onc output,
S. lt cortsist of afitlt adder cirait connected to a Dflip-flop, as slnv'n in Fig. 7.'26. Drive the
stute tuble and slutc diagram of the scquential circuit.
x

Ft,9.7,28

Draw the equivalent ASM chart, leaving the state boxes empy'.
I

Solutlon.
Table 7.1

Present state
i
._J

,I II

a
0
0
0

-l
I
I

L-l

l.
t.
I

Inputs

.ry
00
0l
l0
ll
00
0l
l0
ll

Nert state

Output

.t

[lxanrple 7.r2. Drart,art AStI

rhrr,;:l:'f,!rr,,,, x,ittt 2.8 bit registc,rs
perfonns the subtrrtctiort opentrio,tt
2ls1,,f 2 s c,otnpletttertt nethol,

Rl <- Rt-

Ra

R.1

artt! R6 ant!

&Gpy Bltrtlxtl, Jtrttt,

Solulion.

2003)

InitillSrarc

Rrr*

lnPutA

Rs--lnpu

fa*Ra

+ 2's complemenr of Ru

Borrow<- compternent of carry

Ftg.7.2S

;,.ffi

\'

.tl'lll
a

- ,a !

Solution.

a^*?
-"-\
qx

TE z( + ?
)

I
I

,l

_Link 3

Ex

rl

*I

&-? Qx
TrtrzV$.

ed,\H 1F

ax
drTqX
oo\

-o\ o-l
.-,

?Y=pqx
F19.7.22

outputT'- PQX
Using thc rcalization stcps givcn in scction 7.5, wc frnd that thc conditional
rincc thc o-nly link, path tlrrougM tttttt witfi PQ = I I and takcs thc X = I bronch'
a state B that has
Thcrc arc tluee link paths (lobelcd link 4, link 2, link 3), which tcnninatc in
X=}branch ond temrinates on a state Cin
0 - l. Link I starts with a present slate PQ= 01, takcs
paths'
ilrict e = l.Therefore, the ncxt-state equation for Q thts has 4 terms corrcsponding to the 4 link

Ig
Epex +pox
Gffi@riltrmr
+PAx *

Similarly, one hnk

paYt,I

;=

l) terminate in a state cwith

P=

l,

so

PQX

assignment as
Next state .quuffii of e can be simplified with k-rnap using the unused state
r don't care condition.
.Pa

00 0l ll

rl

3l
F19.7.23

e' =Fg+Fx

+QX

l0

0.

@-

E xarrple

7'r0. convert ile SM charr of Fig. 7.20

to state grapht.

o\

s,lrrtlo''

'l'trc givcn
sM clrart r,rr l ,,1',1 lolr-on.^for
each sratc. J6 is rhc srarring
It has orrc irrpur ,\'ond output
srare.
z uri o.,tprt is l onry in ,iot. s3.
If 'll = 0 is statc sg' z = 0 and
thc ncxt state is J9 itself,
If k = l,
-0, thc next statc is J1 .
If'li-0i'state s2'z=0andthcnextstateisJgwhile

In

forx=l,z=0,thenextsrateis.s2.

{r, ifx=

0, the nctrvork returns to,s9

0therwise, thc next state is.s3.
putput Z is placcd in the statc box J3, therefo
re Z is i
thcnext','[iri itsetr. Fis.7,2r
;';3:rtb'otherwisc,

Jff:'**;:rffijil;ft*:l'jl

I
I

(.

r-7\

nplffi{'

For the EM char,

"rrTn;|fl make therottowing state assignntentfor

A, PQ = 00; B, PQ = 0l
; C, pg 11.
Derive the nexr sh? and
ourpir equati,
oy rracng link paths on
the equatiotu
the isM chsrt.
oni.iirf),on
r.uo,io,u anc!
thrn aron-ti;';;;'u-u"u,r
rhe net*ork;;:o{;::'::^':!o::tu .on

the
t

logic gati.

sinptifi

-]t. f,Vft

'!

when'
t' 'arl

.".r,

Example 7.9. Convert the state g.aphs of Fig.

7. t

8 to SM chart.

o/

iii.a
-t

tl

i--_i
I
I

Fig.7.18

Solution.

I
I
I

I
1

I
I

I
I

ll

-J

I
I
I

..)

'I

t, rt
F19.7.19

Form 4 states boxes for cach state and after each state box put input in decision box and put
conditional output box in the path whereMealy ouputs are I . Fig. 7.19 shows an SM chart for thc
state graph of Fig. 7. I 8.

Exanrple 7.8. obtain a s-late diagram

for a Moore circuit which produces output'1, rrh,
it detects rhe sequence l0l. ot,errapping scquences o* otioru"i.;i;;;;r;;,;r;';;;;:;:

-for the givctr circuit.

Solution.

ltl
0

Fig.7.16

!IT.JT{I COP

-,
(.

(
I

Fi,1.7.17

ff;li:':fil ;}1:1,:1:ll'*i"'^t"5*::?]:*''ne

is placed in the state box since it is tdependent

of input.
Fig. 7.17 shows an SM chart for the state diagram

for each stare. rhe Moore

sutpq

ofFig. 7.16.

i],F[ii'i.
I

/@nn
r-l

-l'

Insecondcase(Fig.7.l3(D))theoutputis l'= |

if8= t, C= I orB =0'A

=t

or8:l,C-0'

Y = BC+AE+ABe

llcnce

= AE+BUe +C'l
= AE+ BQ+C)
=tr+ BC

i
i
I

,frich

is the same

ouput function realized by the ASM chart of Fig.7 .13 (a).

Hence

X and Y are

14icolly equivalent
t^----

@DrawanASMcharttodescribeameaIystatemachinethatdeteclsasequence

at the output tluring the last state of the sequence.

! --A@ffiCserrc a logical I
Figure 7.14 gives thc cdrresponding state diagram for a given sequence detector.
solur
Solutlon.
iI
I

i!,, lotot
,r..

"-t

Fisl

1,.,^.1. .'leaal
, i
I

Ftg.7.14

'lb dcrivc SM cSart fronr Mcaly starc ctiagram, form thrcc statc boxcs for cuch statc l, B and
(.. Aftcr cach stntc box put input in iccisiorr box and put conditiorul output box in thc puth wltcre
lrtcrly ourputs arc l. fig. 7. f5 gir.r thc corrcsponding SM chori for I givcrt dctcctor.

F19.7.15

ffi
Solutlon.

[:xit

Patlr 2

F19.7.12 An SM block

Output Q is alrvays I , so it is placcd in thc statc bo.rcs sincc it do not dcpcntl on i1put. 1.,
7,12 shows thc rcquired SM block with two exit path.
1
I

Errnrpfc 7.6, Figurc 7,13 kt) and 7.13O), represeilts an ASM chartsfor tv'o boolc
function X ond Y show th,ot'thc

F:ft h -:',4-

twtt

tLWlty,cWtg&

(a)

hJ.
:

ore,

F19.7.13

In fint casc (Fig. 7.13 (a)) ftc output

isX- lif A- l orifl -0,8

= I andC- I Hencc

:i:i:,:,
:l

I
tit

Ouput Z is always l, i.e. it is not a function of input variables (A, B, C), thereforc.put
',rrtput Z in state box. Ouput ll/ is I ifl A and B are both I else f l/ is 0.

lf

C=l

andA=0, )'= I andexitpath I istaken.OuputX= l,

the

ifC= 0orA=0andcxitpath

,l rs taken.

'onvert the state diagram of Fig. 7.10 to

4Sj!chart.

s ,>\ ,/'

rr

Solution.

Fig. 7.1 l shows an ASM chart for

*, ,[i;Ht*m

of Fig. 7. 10.

Example 7.5. Construcl an ASM btock that has 3 input l,ariables (A, B, C) 4 ttutlttrt
wriobles (P Q, R, S) aud 2 exit paths. For this block, output Q is alv'ays I, cuul P is I iJJ' I " 0.
tt A and B are 0 or if(A = I ond C J q,R = / and uit path 2 is taken. IfA and C ara I or
Jl-= 0 and B - l),.S = / and exit path.l ts taken.

tt'
I

,,r,.ln""tl':;

ill ;tS fJ

Fig.7.8

li'j:'.TIi

'i'!,t,',;i.[1','..'.'i'f

f j13:T,q.l:::::r,rvir

be .r ,regardrcss

rr,*,rruc or
,?.,i';,i"i,1;;:;;1;;,,:,Ttk* 3,'ff::i,*"-rl':,j;lliiit'J"l;[:'ji:iiilJ],;i':I#
,,,
;:,,; il ;::fi.),:,,: :;nH:ii:j:;,1,i,:

J:;:llTll"Ii3

If D is 0 ttrcn outpuf::will
bc .l
llxnn:otc 7.3. Coust^tct

Y z), und

t''

un rn, ,,!?:! tly,t.has.J

input *r,::!^tS,(A, B,
2 cxir rxttrn..t'",, ti,r'ii"i*'
C), 4 ourltuts (W, X,
o:tr:r:
z
y- t artdcxttl,o,i,'itr.tuken. t, otrroy,r), ynct
t ,/rA ant* are botrt r. rf

:fif, ":.0

y'c-'ior,4 -0,x^w.t1
iinae:itpattt

hg. z.e An sM Bto.k&lt

2 is takcti,

I
/)It'l
r.-r
t

.l

rti

.!

:
'l
I

!'e

,ffi

rlif

l..._

4. For each of these link paths, find a tcrm that is t when th'e link path is followed. For
example, to *ritc the cxpression for next statc of 8, we consider link path I n'hich is start in
stateZp(AB =01), takes theX= I branch, andends instate ZOUB = I l), so the next state
of8 has atermA'BX.

t.f
: l.

..I I
ii

Link Path

rbi

;l
il',rl

.{

:
t

..r
I

v()

ll

I
i
I
I
a

l'

illg
I
I

.rlc

Fig.7.6
4. The expression for thc next state of Q is formed by OIting togetltc'r all the tcnl$ fotrnd
stcp 3.
5.
6.

Sinrilarly, thc cxprcssion for output can bc rcad dircctty fronr the ASN'l cltlr t.
Find o sinrplilic4 cxprcssion for output and ncxt-strtc cquatiotrs rvith a t-tturll trsittg thc
unuicd statc ossignmcnt as n dott't carc condition'

7. Rcslizc thc SM chart using gotcs and flip-flops.

Errnrple 7,1, Obtalrt
ln conditlon box.

thc ASM

in

ctnrtforlollowlngfitnctiott,

i,f

*'a Mil l,ut x'lnla c.tpres.siott

Z=A+B'C
Solutlon.

.l

l.r
ty.

J-r
.l

t!
I

''0'
nd

Flg.7.7
+
placed in the
ASM chart for Z = A *B,C contain onlylne state box. Condition A B'C is
decision box and Z in conditional output box.
is placed
Errmple 7,2, Draw flttjWhartforfoltowingfunction, deach input variable

in the decision

box.

Z-

AB' + C' D'

Similarly, Fig. 7.5 (c) shorvs that Z=

which is the same ourpur funcrion

| if AB t AC= l. Ilence, Z= A (B + C)
= AB + )g

rearized by the ASM chart of Fig.

7.5.

nrs t check,{ i f ,4 s ze r o z rrirn

gnd jtiln
j,l'.',ii
b
I,ff.,..,T# ili; l j l?l.T ?:,,.i: l j:
_b_o1,
iiJ''5
:'
i
.oi
i
t=
C= o,:n:n
il'fi
0 then our:ur
outnltf witl
h. '0' Lo^^..^^
:, r and B
*rllo.
b..uur.-z{r is
i, urro o.'#J,xr,trtlTf;;*TJ.|*.,,!irf'J

in

'

iil

l.

Tj:i:lffi;::'fi J;: {!! :i }jr".,,j*:i;+:;Tj:?\T;,');:TtrlXil1iffi

I,i ! !:,ld_n ycond tio n box Fi r check B, ir B is l
i#H;"1.T:ili:Hi:*:':,i:
zero
because both temu arezero.lf
;.
AC: l, Zwill be l.
i

last case, we may pur whofe

boolean
-.In
AB +
conditional output box.
"*pr"riion

7.4.

AC incondition box and Z irJ

CONVERSION OF A STATE
DIAGRAM TO AN ASAA CHART

*,,."l|X,ll:ilff::*ilu|1ji:'T;"'diagram
exacrrv

rs

on..*it fitrr crcnned c;;il

:'j:

ormachine, bur

ce

rrair'

*r.,

nrusr be ronowed

ftil;,il;i'ffT,',ilTifilifialil;;ff' ;.

Mealy ntacltirte' In casc of Mcaty

nrachine, output is a frrrrctio'.f
b,t' prcsc't statc
Iror c.ttstructio' .fASv
tr"n-ilnr
Mcaly srarc diagr'n\ \r,c shourcilirilorv
ltiii.
rtrc

arrcJ

folowi'g
.

l.

Rcprcscnt cach statcs by

starc
2 Put input in dccision box a{lcr coch
statc box.
oulput
in corrditional outpur boxcs
sincc thcy depcnd
'ppc'r
,xf tH,y

boxcs.

o' botl

r1c starc

4' Meary circuit output writtcn

o'ry wrrcn it is cquar to ,r , i e.,
truc.

5' Dcpending on varue of input

connect the path to ncxt
state box.
fr{oore mochlne' ln case
of Moore machine, output
is a function of the present
For conshuction ofAsrur
state onry.
crrirt n*'rta*r.
*r rr,orta rorr"*,r,.
fortowing
'v"vw

l.

rodilil

Represent each states

by state
The Moone output are praced

boxes.

steps.

t
I

'i I
in the state boxes since they
do not depend on the input. ii
3. After each state box put
I,
the input in decision box.
L,
4' Depending on varue of input
connect the path to next
state box.
[-r
ll
REAIfZATfON OF ASi,l
Lii
CHARTS
Realization ofASM charu
u', ri-it., to the rnethods used
to rearize state diagrarn
t'ft
I
ut
ihe
tn,
or*i
r#rq*,ion for a nip-nop irgares
fr1,-"rffif;:"ffj;" "n
and
e

7,5.

*'l

"i.ri",

l'

The first step is to make

a suitabre state assignment
for...h ro,r.
2 Search all the states for which
e is one.
3' For each of these states,
at of the rink paths that read
inro the stare.

'nd

tl
I

I
I

Branch 2

f
I
I

-1
,l

,l

-'l

tl

AIJ

tt'l
.l

Fls.7.a (b)

IJ
tl )

cj
il

7,9,

EQUIVALENT AsM

CHARTS

'

I'

'

',

ASM charts arc not uniquc, it nray havc nrorc tltan onc cquivalcnt fornr Fig. 7.5 shorvs tlrrcc
cquivalentASM charts for conrbinutional nctwork Z-A $ ! q.

I
;

Flg. 7.5 Equlvalent ASM charts lor

Zo A (8 + Q

|
ASM chart for cornbinational network contain only onc state box. The output Z= | if A =
arrd either I or Cequal to l, as shown in Fig. 7.5 (c).
Fig.7.5 (D)shows an equivalent ASM chart in which Z- | if either AB = | o: AC= l'

_ _ -__ ,.,^e.rr,tc)

::]D,ffi'I;|r,Tj,;: j::*:j:n:n1b."_

wl$

true.and farse bra'ches. Boorc.ah

condirion

il;"'.;;';,Hffi:i:;rgnals. The

dccisron box must

inrrcr foilbrv
fnllh.,, and
--r L^
be associated *,ith a state box.

'i

(iii) cottctitiottat

A.Fo,irli't"ffIl,ii!;il.

bo-v.
is sh.orv'
'urptit
Fig. 7.3 is a rectangurar
bo'x rvith curved ends' It
contain conditional oufput t;r;.
conditionar ourpur crepcrcrs
(he state of the systc'nt
borrr
and the inputs. T}erefoie th. .on,litional
output signals are solrretinrc.s
knowrt as Mealy outputs. A conditional
outpur nrusr follorv a tlecisitln
bo.x.

i'

,.

(ltlnrlit ional

()ulpui l.lsr

(iv) AsM Btock.^sM

0,,.[?;';.,:;:lillTi[{f-i,firon,

sratc box rvitrr onc or

dccisiort boxcs and cortditionor
Ci*.r associatcd ,"irhtthrt:;rl. an
ntpiur".r. has onc crrrarcc
',orc
path and one or ntorc cxit
paths. nn nsrra chart consiri,
oron. o, n.,or. iir',-.-r.o,*.ctcd
Ilxccution ofsM block it
blocks.
t"q*"tii
concurrcntprocess., ia."r, whercas.*e.r,ion orinrrru.tlon.fruirrrin sM brock is

.,

.r

I
li

,, ,,1,?fiff:
"

ch and tink

poth.

Apat;'ft'"rrflfilrilTlck

L,
rrom enrrancc ro exit is
rererred ro

Basic element for branching

is decision box. After
decision box we get two
false' Depending upon
exit path, true or
condition-one can branch
itself upwarcl or don*+,ard.

(l
tl

t:

I
I

.t

i -.-l

//

r-\
/ ''r
to VHD|

tl
rj
-

.-1
rt

ATGORITHMIC STATE

'{

rl

il
n:
I q --t
;l t
|

r.,D

_l

t
I
I
l

i
!
I

i
d

I
i

7.1. Asn^ GHART,Algorithmic

nuchinc' or sirnply state nnchine is the another name

netrvork is used to control a digital systetn rvhich carries
l:rvcn to sequential netrvork. Sequential
(AsN'l chart) or state nrachine
frrr a stcp-by-step proceclure. Algorithnric srate nuchine charts
rese nrblcs
uscful in hardrvarc design of cligital systenl. ASM chart
e lnrts (SM charts) arc flow charr,
cotttain inplicit tirrring
r convcntional llorv chart, but it is dill'crcnt liorn flowclurt. ASM cltrtt
physical ltardwarc and oft'crs scvcral
[rformation. It should bc notcct that ASM charts rcprcscnt
ASM stands for

state

rrlvarttagcs.

by irrspcction of thc sM chltrt'

opcration of a cligital systcnl con bc casily unclcrstitncl
2. ASM cltarts rcprcsctlt physicol lrardwarc
groph, oncl it lcads dircctly to u ltardwlrc
3. 't'hc AsM charts urc cquivolcnt to u stutc

l.

.J

tI
I

i
I
1

{I

II

.5

I
I

:l../
rl I
I

.,

a. fittni"jl,, .on'b. dcscribcd

;: il;,;r*';;;

scqucntial circuits'
rhc opcration of both combinational ond

sevcral equivalent fornr'

to undcrstana ano cm bcconverted into
output table'
be equivalcntly cxpressed as a state nnd
or.. aigtal svstem. It is an abstract description

.ori.,

6. 'l'he AsM .t urt *uy

a a.sqripti;" 6;r;;.in;*ion
does, but not how it is donc'
r,r the ,u*rt,rru, iiilescribes what a syitem
point of thc hardware synthesis process' Any
The ASM chart can be use{'as ttb slarting

' :#ilffi;

in'more
givenASM chartrnay be implcmented in hardware

7.2.

ltt'

CHART
PRINCIPAL COMPONENT OF AN ASIA

At
a state box' It is a rectangular box'
(f) stateDox. The state of the system irreprcsentedby
hand corner the state
is siro*,
rhe top left-hand.o*., the name of rtui,
state box, the output signals are listed'

whili::*::ij,ltn,

.,rr,,,i"t

"i;;i";;:wt,ttii,rtt

Stote Assignnrcnt
OutPut Llst

i,

r,.i

luo:1*
'aat

or Rcgister OPcntion

Flg.7.1 State box.