11/20/2014

vlsi world: Verilog Code for RAM & ROM

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vlsi world
Saturday, 4 February 2012

Verilog Code for RAM & ROM

Verilog code for single-port RAM in read-first mode.
module raminfr (clk, en, we, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule

verilog code for a single-port RAM in write-first mode.

module raminfr (clk, we, en, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[4:0] read_addr;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule

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2012 (35)
February (28)
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verilog code for single-port RAM in no-change mode.

Verilog Code for FSMs

Verilog Code for RAM & ROM

module raminfr (clk, we, en, addr, di, do);

input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)

http://vlsiworld-asic.blogspot.in/2012/02/verilog-code-for-ram-rom.html

Verilog code for comparator

Verilog code for adders/subtractors
Verilog code for different MUX
Verilog codes for different Shift-registers
verilog code for ACCUMULATOR
Verilog Codes for different COUNTERS
Verilog code for a tristate element
Verilog Code for different LATCHES

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vlsi world: Verilog Code for RAM & ROM

begin
if (en) begin
if (we)
RAM[addr] <= di;
else
do <= RAM[addr];
end
end
endmodule

Verilog code for a 4-bit register

verilog code for different FLIP-FLOPS
Verilog code for encoder using ASSIGN
Verilog Code for PRIORITY ENCODER
using IF-ELSE
verilog code for ENCODER using CASE
verilog code for ENCODER using IFELSE
verilog code for DECODER using
Assign statement

Verilog code for a single-port RAM with asynchronous read.

module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule

Verilog code for a single-port RAM with "false" synchronous read.

module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
do <= ram[a];
end
endmodule

Verilog code for DECODER

January (7)

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Verilog code for a single-port RAM with synchronous read (read through).
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule

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Verilog code for a single-port block RAM with enable.

module raminfr (clk, en, we, a, di, do);
input
clk;

http://vlsiworld-asic.blogspot.in/2012/02/verilog-code-for-ram-rom.html

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vlsi world: Verilog Code for RAM & ROM

input
en;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule

Verilog code for a dual-port RAM with asynchronous read.

module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule

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Verilog code for a dual-port RAM with false synchronous read.

module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[3:0] spo;
reg
[3:0] dpo;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
spo = ram[a];
dpo = ram[dpra];
end
endmodule

Verilog code for a dual-port RAM with synchronous read (read through).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;

http://vlsiworld-asic.blogspot.in/2012/02/verilog-code-for-ram-rom.html

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vlsi world: Verilog Code for RAM & ROM

output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
reg
[4:0] read_dpra;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule

Verilog code for a dual-port RAM with enable on each port.

module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);
input
clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;
reg
[3:0] ram [31:0];
reg
[4:0] read_addra, read_addrb;
always @(posedge clk)
begin
if (ena) begin
if (wea) begin
ram[addra] <= dia;
end
end
end
always @(posedge clk)
begin
if (enb) begin
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule

Verilog code for a ROM with registered output.

module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4b0000: data <= 4b0010;
4b0001: data <= 4b0010;
4b0010: data <= 4b1110;
4b0011: data <= 4b0010;
4b0100: data <= 4b0100;
4b0101: data <= 4b1010;
4b0110: data <= 4b1100;
4b0111: data <= 4b0000;
4b1000: data <= 4b1010;
4b1001: data <= 4b0010;
4b1010: data <= 4b1110;
4b1011: data <= 4b0010;
4b1100: data <= 4b0100;
4b1101: data <= 4b1010;
4b1110: data <= 4b1100;
4b1111: data <= 4b0000;

http://vlsiworld-asic.blogspot.in/2012/02/verilog-code-for-ram-rom.html

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vlsi world: Verilog Code for RAM & ROM

default: data <= 4bXXXX;
endcase
end
endmodule

Verilog code for a ROM with registered address.

module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
reg [4:0] raddr;
always @(posedge clk)
begin
if (en)
raddr <= addr;
end
always @(raddr)
begin
if (en)
case(raddr)
4b0000: data = 4b0010;
4b0001: data = 4b0010;
4b0010: data = 4b1110;
4b0011: data = 4b0010;
4b0100: data = 4b0100;
4b0101: data = 4b1010;
4b0110: data = 4b1100;
4b0111: data = 4b0000;
4b1000: data = 4b1010;
4b1001: data = 4b0010;
4b1010: data = 4b1110;
4b1011: data = 4b0010;
4b1100: data = 4b0100;
4b1101: data = 4b1010;
4b1110: data = 4b1100;
4b1111: data = 4b0000;
default: data = 4bXXXX;
endcase
end
endmodule

Posted by kumar at 01:34

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2 comments:
Manish Kumar Yadav SEO 1 August 2014 03:05
Thanks for sharing this post.
Om Nanotech offer complete range of Non-ECC DRAM modules. We are DRAM Components
Supplier Distributor in India Delhi/NCR.
Reply

Anonymous 16 November 2014 21:30

thanx a lot it was really helpful
Reply

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