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Ram and Rom Verilog

The document contains Verilog code for various memory components including single-port and dual-port RAMs as well as ROMs. The RAM codes demonstrate different read/write modes such as read-first, write-first, and no-change. Additional features shown include asynchronous/synchronous reads, enables, and registered outputs. The ROM codes implement a simple lookup table using a case statement with registered outputs and addresses.

Uploaded by

Abhishek Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
2K views

Ram and Rom Verilog

The document contains Verilog code for various memory components including single-port and dual-port RAMs as well as ROMs. The RAM codes demonstrate different read/write modes such as read-first, write-first, and no-change. Additional features shown include asynchronous/synchronous reads, enables, and registered outputs. The ROM codes implement a simple lookup table using a case statement with registered outputs and addresses.

Uploaded by

Abhishek Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Verilog Code for RAM & ROM

Verilog code for single-port RAM in read-first mode.


module raminfr (clk, en, we, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
do <= RAM[addr];
end
end
endmodule

------------------------------------------------------------------------------------verilog code for a single-port RAM in write-first mode.


module raminfr (clk, we, en, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[4:0] read_addr;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule
-----------------------------------------------------------------------------------------------verilog code for single-port RAM in no-change mode.
module raminfr (clk, we, en, addr, di, do);
input
clk;
input
we;
input
en;
input [4:0] addr;

input [3:0] di;


output [3:0] do;
reg
[3:0] RAM [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (en) begin
if (we)
RAM[addr] <= di;
else
do <= RAM[addr];
end
end
endmodule
-------------------------------------------------------------------------------------------------------Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
--------------------------------------------------------------------------------------------------------Verilog code for a single-port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[3:0] do;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
do <= ram[a];
end
endmodule
---------------------------------------------------------------------------------Verilog code for a single-port RAM with synchronous read (read through).
module raminfr (clk, we, a, di, do);
input
clk;
input
we;
input [4:0] a;

input [3:0] di;


output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule
----------------------------------------------------------------------------------Verilog code for a single-port block RAM with enable.
module raminfr (clk, en, we, a, di, do);
input
clk;
input
en;
input
we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
always @(posedge clk)
begin
if (en) begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule

Verilog code for a dual-port RAM with asynchronous read.


module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule

Verilog code for a dual-port RAM with false synchronous read.


module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[3:0] spo;
reg
[3:0] dpo;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
spo = ram[a];
dpo = ram[dpra];
end
endmodule

Verilog code for a dual-port RAM with synchronous read (read through).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input
clk;
input
we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg
[3:0] ram [31:0];
reg
[4:0] read_a;
reg
[4:0] read_dpra;
always @(posedge clk)
begin
if (we)
ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule

Verilog code for a dual-port RAM with enable on each port.


module raminfr (clk, ena, enb, wea, addra, addrb, dia, doa, dob);
input
clk, ena, enb, wea;
input [4:0] addra, addrb;
input [3:0] dia;
output [3:0] doa, dob;
reg
[3:0] ram [31:0];
reg
[4:0] read_addra, read_addrb;
always @(posedge clk)
begin
if (ena) begin

if (wea) begin
ram[addra] <= dia;
end
end
end
always @(posedge clk)
begin
if (enb) begin
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule

Verilog code for a ROM with registered output.


module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4 b0000: data <= 4 b0010;
4 b0001: data <= 4 b0010;
4 b0010: data <= 4 b1110;
4 b0011: data <= 4 b0010;
4 b0100: data <= 4 b0100;
4 b0101: data <= 4 b1010;
4 b0110: data <= 4 b1100;
4 b0111: data <= 4 b0000;
4 b1000: data <= 4 b1010;
4 b1001: data <= 4 b0010;
4 b1010: data <= 4 b1110;
4 b1011: data <= 4 b0010;
4 b1100: data <= 4 b0100;
4 b1101: data <= 4 b1010;
4 b1110: data <= 4 b1100;
4 b1111: data <= 4 b0000;
default: data <= 4 bXXXX;
endcase
end
endmodule

Verilog code for a ROM with registered address.


module rominfr (clk, en, addr, data);
input
clk;
input
en;
input [4:0] addr;
output reg [3:0] data;
reg [4:0] raddr;
always @(posedge clk)
begin

if (en)
raddr <= addr;
end
always @(raddr)
begin
if (en)
case(raddr)
4 b0000: data =
4 b0001: data =
4 b0010: data =
4 b0011: data =
4 b0100: data =
4 b0101: data =
4 b0110: data =
4 b0111: data =
4 b1000: data =
4 b1001: data =
4 b1010: data =
4 b1011: data =
4 b1100: data =
4 b1101: data =
4 b1110: data =
4 b1111: data =
default: data =
endcase
end
endmodule

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

b0010;
b0010;
b1110;
b0010;
b0100;
b1010;
b1100;
b0000;
b1010;
b0010;
b1110;
b0010;
b0100;
b1010;
b1100;
b0000;
bXXXX;

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