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Model Sim The Main Purpose of This Lab Is To Understand The The The Verilog Language With A Very Simple Example of Full Adder

This lab aims to implement a full adder in Verilog and study the effects of gate delays. Students will use ModelSim to enter Verilog code for a full adder in one file and testbench code in another, then compile and simulate the design. The simulation output will be compared to the full adder truth table to verify functionality.

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Muhammad Kamran Akram
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43 views

Model Sim The Main Purpose of This Lab Is To Understand The The The Verilog Language With A Very Simple Example of Full Adder

This lab aims to implement a full adder in Verilog and study the effects of gate delays. Students will use ModelSim to enter Verilog code for a full adder in one file and testbench code in another, then compile and simulate the design. The simulation output will be compared to the full adder truth table to verify functionality.

Uploaded by

Muhammad Kamran Akram
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lab 03

Objective: Implementation of full adder & study the effects of gates delays
Tools:-
Model sim
Purpose:-
The main purpose of this lab is to understand the the the verilog language
with a very simple example of full adder.
Full Adder
Circuit Diagram Truth Table


Double click on modelsim
from desktop .
Enter code from one file
name fulladder.

Create another file which
name tb_fulladder and paste
the code which given you as
manual.

Complie the code as given below.then simulation starts click ok.

Then you click add and all items in region
icon.






After all click on run button and wave from
show .
You are compare with truth table .

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