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Fabrication of CMOS

The document describes the key steps in the CMOS fabrication process including deposition of a nitride layer, growth of a field oxide layer, addition of a polysilicon gate, implantation of sources and drains using select masks for p-type and n-type regions, addition of contact cuts through insulation, and the use of two metal layers for interconnects with vias between layers. The MOSIS SCMOS process is specified but does not allow stacked vias for multilevel interconnects.

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prasanna810243
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17 views

Fabrication of CMOS

The document describes the key steps in the CMOS fabrication process including deposition of a nitride layer, growth of a field oxide layer, addition of a polysilicon gate, implantation of sources and drains using select masks for p-type and n-type regions, addition of contact cuts through insulation, and the use of two metal layers for interconnects with vias between layers. The MOSIS SCMOS process is specified but does not allow stacked vias for multilevel interconnects.

Uploaded by

prasanna810243
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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CSE 462: VLSI Design J.

Brockman, University of Notre Dame 2000


CMOS Fabrication Process
and
MOSIS SCMOS Mask Layers
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
CMOS Inverter
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
P-Type Substrate and N-Well
P-type substrate
NMOS devices
go here
N-well
PMOS devices
go here
N-well mask
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Active Area
deposited
nitride layer
active mask defines
p-type and n-type
mosfet locations
(drain-gate-source)
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Field Oxide Growth
field oxide
gate oxide
Thick field oxide
electrically isolates
transistors
Nitride prevents field
oxide growth
Thin gate oxide grown
after nitride removed
o
2
o
2
o
2
o
2
o
2
o
2
o
2
o
2
o
2
o
2
SiO
2
formation consumes Si
Si-SiO
2
interface below
original Si surface
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Polysilicon Gate
poly mask
added to layout
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
P-Select Mask and N-Type
Source/Drain Implant
n-type
implant
p-select covers p-type
source/drain regions
select mask must
overlap active areas
n-type ion implant
creates n-type
source/drain regions
high temperature
anneal repairs silicon
lattice and causes
diffusion of implanted
ions
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
N-Select Mask and P-Type
Source/Drain Implant
finished mosfets p-type implant both select masks added
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Contact Cuts
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Metal 1
non-planar surface
CSE 462: VLSI Design J. Brockman, University of Notre Dame 2000
Via 1 and Metal 2
Multilevel interconnect fabrication
processes planarize between layers
(expensive)
MOSIS SCMOS does not allow
stacked vias

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