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Digital Systems Design

This document discusses finite state machines (FSM) and their application to digital systems design. It provides examples of FSM implementations for sequence detection and serial addition. FSM models are presented using state diagrams, state tables, and logic circuit diagrams. Mealy and Moore machine models are examined for their use in serial addition circuits.

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89 views

Digital Systems Design

This document discusses finite state machines (FSM) and their application to digital systems design. It provides examples of FSM implementations for sequence detection and serial addition. FSM models are presented using state diagrams, state tables, and logic circuit diagrams. Mealy and Moore machine models are examined for their use in serial addition circuits.

Uploaded by

amitkaller
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ECEN 248 Introduction to Digital

Systems Design (Spring 2008)


(Sections: 501, 502, 503, 507)
Prof. Xi Zhang
ECE Dept, TAMU, 333N WERC
http://dropzone.tamu.edu/~xizhang/ECEN248
FSM for Sequence detector (Mealy Type)
Unlike the Moore type machine, the
output depends not only the current
state, but also the current input.
Figure 8.22. Sequences of input and output signals.
Clock cycle: t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
w : 0 1 0 1 1 0 1 1 1 0 1
z : 0 0 0 0 1 0 0 1 1 0 0
Sequences of input and output signals
Figure 8.23. State diagram of an FSM that realizes the task in
Figure 8.22.
A
w 0 = z 0 =
w 1 = z 1 = B
w 0 = z 0 =
Reset
w 1 = z 0 =
State diagram of an FSM
A: starting state, also the state after an
input w=0 is applied.
B: w=1 in immediately preceding clock cycle.
Figure 8.24. State table for the FSM in Figure 8.23.
Present
Next state Output z
state
w = 0 w = 1 w = 0 w = 1
A A B 0 0
B A B 0 1
State table for the FSM
A
w 0 = z 0 =
w 1 = z 1 = B
w 0 = z 0 =
Reset
w 1 = z 0 =
Figure 8.25. State-assigned table for the FSM in Figure 8.24.
Present
Next state Output
state
w = 0 w = 1 w = 0 w = 1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1
State-assigned table for the FSM
Present
Next state Output z
state
w = 0 w = 1 w = 0 w = 1
A A B 0 0
B A B 0 1
Derivation of the logic expressions
Y = D = w;
z = wy;
Present
Next state Output
state
w = 0 w = 1 w = 0 w = 1
y Y Y z z
A 0 0 1 0 0
B 1 0 1 0 1
Figure 8.26. Implementation of FSM in Figure 8.25.
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1
0
1
0
1
0
1
0
Clock
y
w
z
(b) Timing diagram
Clock
Resetn
D Q
Q
w
z
(a) Circuit
y
Implementation of FSM
Circuit that implements the specification
Clock
Resetn
D Q
Q
w
z
(a) Circuit
y
D Q
Q
Z
Figure 8.27. Circuit that implements the specification in Figure 8.2.
Figure 8.27. Circuit that implements the specification in Figure 8.2.
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1
0
1
0
1
0
1
0
Clock
y
w
z
(b) Timing diagram
1
0
Z
Circuit that implements the specification
Break page between Ch 8.3 and 8.5
Figure 8.39. Block diagram for the serial adder.
Sum A B + =
Shift register
Shift register
Adder
FSM
Shift register
B
A
a
b
s
Clock
Example of the serial adder
A = a
n-1
a
n-2
a
0
B = b
n-1
b
n-2
b
0
A = s
n-1
s
n-2
s
0
= A + B
Figure 8.40. State diagram for the serial adder FSM.
G
00 1
11 1
10 0
01 0
H
10 1
01 1
00 0
carry-in 0 =
carry-in 1 =
G:
H:
Reset
11 0
ab s ( )
State diagram for the serial adder FSM
Figure 8.41. State table for the serial adder FSM.
Present
Next state Outputs
state
ab =00 01 10 11 00 01 10 11
G G G G H 0 1 1 0
H G H H H 1 0 0 1
State table for the serial adder FSM
G
00 1
11 1
10 0
01 0
H
10 1
01 1
00 0
carry-in 0 =
carry-in 1 =
G:
H:
Reset
11 0
ab s ( )
Figure 8.42. State-assigned table for Figure 8.41.
Present
Next state Output
state ab =00 01 10 11 00 01 10 11
y
Y s
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
State-assigned table for the serial adder
Present
Next state Outputs
state
ab =00 01 10 11 00 01 10 11
G G G G H 0 1 1 0
H G H H H 1 0 0 1
Figure 8.43. Circuit for the adder FSM in Figure 8.39.
Full
adder
a
b
s
D Q
Q
carry-out
Clock
Reset
Y y
Circuit for the serial adder
Figure 8.44. State diagram for the Moore-type serial adder FSM.
H
1
s 1 =
Reset
H
0
s 0 =
01
10
11
11
01
10
G
1
s 1 =
G
0
s 0 =
01
10
00
01
00
10
11
00
00
11
State diagram for the serial adder (Moore-type)
Figure 8.45. State table for the Moore-type serial adder FSM.
Present
Nextstate
Output
state
ab =00 01 10 11 s
G
0
G
0
G
1
G
1
H
0
0
G
1
G
0
G
1
G
1
H
0
1
H
0
G
1
H
0
H
0
H
1
0
H
1
G
1
H
0
H
0
H
1
1
State table for the Moore-type serial adder
H
1
s 1 =
Reset
H
0
s 0 =
01
10
11
11
01
10
G
1
s 1 =
G
0
s 0 =
01
10
00
01
00
10
11
00
00
11
Figure 8.46. State-assigned table for Figure 8.45.
Present
Nextstate
state ab =00 01 10 11
Output
y
2
y
1
Y
2
Y
1
s
00 0 0 01 0 1 10 0
01 0 0 01 0 1 10 1
10 0 1 10 1 0 11 0
11 0 1 10 1 0 11 1
State-assigned table serial adder
Present
Nextstate
Output
state
ab =00 01 10 11 s
G
0
G
0
G
1
G
1
H
0
0
G
1
G
0
G
1
G
1
H
0
1
H
0
G
1
H
0
H
0
H
1
0
H
1
G
1
H
0
H
0
H
1
1
Figure 8.47. Circuit for the Moore-type serial adder FSM.
Full
adder
a
b
D Q
Q
Carry-out
Clock
Reset
D Q
Q
s
Y
2
Y
1
Sum bit
y
2
y
1
Circuit for the Moore-type serial adder FSM

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