4 I/P or Gate: Module OR4 (A, B, C, D, w1, w2, Y) Output w1, w2, y Input A, B, C, D or (w1, A, B) or (w2, C, D) or (Y, w1, w2) Endmodule
4 I/P or Gate: Module OR4 (A, B, C, D, w1, w2, Y) Output w1, w2, y Input A, B, C, D or (w1, A, B) or (w2, C, D) or (Y, w1, w2) Endmodule
module OR4(a,b,c,d,w1,w2,y);
output w1,w2,y;
input a,b,c,d;
or(w1,a,b);
or(w2,c,d);
or(y,w1,w2);
endmodule
4 I/P AND GATE
module AND4(a,b,c,d,w1,w2,y);
output w1,w2,y;
input a,b,c,d;
and(w1,a,b);
and(w2,c,d);
and(y,w1,w2);
endmodule
4 I/P NAND GATE
module NAND4(a,b,c,d,w1,w2,y);
output w1,w2,y;
input a,b,c,d;
nand(w1,a,b);
nand(w2,c,d);
nand(y,w1,w2);
endmodule
4 I/P NOR GATE
module nor4(a,b,c,d,y);
output y;
input a,b,c,d;
nor(y,a,b,c,d);
endmodule
3 I/P NOR GATE
module NOR3(a,b,c,y);
output y;
input a,b,c;
nor(y,a,b,c);
endmodule
HALF ADDER
module half_adder_11(a,b,sum,cout);
output sum,cout;
input a,b;
xor(sum,a,b);
and(cout,a,b);
endmodule
FULL ADDER
module FULL_ADDER_11(a,b,c,sum,cout,w1,w2,w3);
output sum,cout,w1,w2,w3;
input a,b,c;
and(w1,a,b);
and(w2,b,c);
and(w3,c,a);
xor(sum,a,b,c);
or(cout,w1,w2,w3);
endmodule