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Dell d531 Quanta Jx6 MGD Rev-D3b - Pp04x - Daojx6mb8d0 Revd

This document provides a system block diagram and index for the JX6 MGD-Integrated system. The 3-page diagram shows the various components and connections in the system, including the CPU, chipsets, memory, ports, and peripherals. The index lists 58 pages that provide more details on the individual components and circuits. Power states, power rails, USB ports, and PCI/PCIe configurations are also outlined.

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Danilo Nunes de Araujo

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0% found this document useful (0 votes)

318 views89 pages

Dell d531 Quanta Jx6 MGD Rev-D3b - Pp04x - Daojx6mb8d0 Revd

Uploaded by

Danilo Nunes de Araujo

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

You are on page 1/ 89

5

Quanta Project Name: JX6

Dell Project Name: MGD Lite
2007-03-01

REV : D3B
A00/X-Build Stage

Title

QUANTA
COMPUTER
COVER PAGE

Size

Document Number
MGD

Date:

Friday, March 02, 2007

Rev
3A
Sheet
1

JX6 MGD-INTEGRATED

SYSTEM
PG 43
RESET CIRCUIT
POWER SW

JX6_PCB

PG 42

CPU HDT
DEBUG PORT
PG 10

CLOCK

AMD S1

ICS951462

Turion 64 Rev.F Dual-Core/

Sempron Rev.F Single-Core

PG 17,18

PG 7

Dual-Core 35W / Single-Core 25W

CH2 DDR II 533/667/800 MHz

DDR2-SODIMM2

DC/DC

PG 47

+3.3V_ALW/+5V_ALW/+15V_ALW

BATT
CHARGER

PG 46

AC/BATT
CONNECTOR

PG 51

PG 42

VCC_NB

REGULATOR

PG 48

+1.8V_SUS/+1.2V_VCCP
+1.5V_RUN/+0.9V_DDR_VTT

PG 8,9,10,11

DDR2-MEMORY DEVICE
8MX16X4 84-PIN FBGA

DVI

533 MHZ DDR II

PG 16

USB2.0 (P6)

DOCKING
CONNECTOR

CARDBUS/1394
OZ711EZ1TN
PG 32

PG 36
S-Video CONN
PG 22

HD-AZALIA
SATA

SATA - HDD
PG 27

SB600

AUDIO/AMP

MDC

Side External USBX2

PG 33
Rear External USBX2
PG 33

USB2.0 (P0,P1)

RJ45/Magnetics
PG 31

33MHz PCI
USB2.0 (P4)
IDE

PG 31

MINI-CARD
WLAN
PG 35

PG 12,13,14,15,16

D-Module
PG 27

+3.3V_LAN

TVOUT
PCIE(L1)

A_LINK

PI3L500

PG 30

465 FCBGA

VGA
DVI

E-Switch

BCM 5755M

PCIE(L2)

RS690

LVDS

Panel CONN.
PG 20

CRT CONN.
PG 21

VGA

HT_LINK

PG 50

(638 S1g1 socket)

PG 17,18

CPU VR

REGULATOR

CH1 DDR II 533/667/800 MHz

DDR2-SODIMM1

549 BGA

STAC9205
PG 28

PG 34

S/PDIF

USB2.0 (P8)
USB2.0 (P2,P3)
USB2.0 (P7)

RJ11
for Dock
PG 36

PG 23,24,25,26
LPC

SPI

Tip
Ring
PG 34

Audio
Jacks
PG 29

Bluetooth
PG 41

SIO

ECE5018
Expander
USB 2.0 Hub(4)

MEC5025
128KB Flash
TMKBC

128 Pins VTQFP

PG 38

SPI
Serial Port

EMC4001
PG 19

FLASH
SST25VF016B

PG 33

Keyboard ECE1077
Controllor
PG 37

128 Pins VTQFP

PG 39

FAN & THERMAL

PG 37

Keyboard
D

PS/2
Touchpad/
Stick point
PG 41

PG 40
USER
INTERFACE
PG 40
5

Title

QUANTA
COMPUTER
System Block Diagram

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet

2
8

INDEX
Pg#

Schematic Block Diagram

Front Page
Merom

5-10

Crestline

11-14

ICH8M

15-16

DDRII SO-DIMM(200P)

17
18-23

Control
Signal

S0/M0

S3/M1

S4/M1

S3/
M-off

S4/
M-off

S5/
M-off

+5V_ALW
+3.3V_LAN

Clock Generator
VGA
LCD Conn. & SSP

CRT Conn

SATA & IDE Conn

PCCARD/Conn & 1394

Express Card & Smart Card

Mini Card

MDC Conn.

SIO (MEC5025)

SIO (MEC5018)

SERIAL PORT & USB

Flash ROM, RTC & ECE1077

TP,BT & FIR

Switch,Keyboard & LED

FAN & Thermal

+1.8V_SUS
+0.9V_DDR_VTT
+5V_SUS
+3.3V_SUS
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.25V_RUN

+1.5V_RUN

38-39

Audio CODEC(STAC9205)/Phone Jack

40-41

LOM (Nineveh)/Switch

42-43

Docking Conn/Q-Switch

+3.3V_ALW

45-46

Power States
Power Rail

Description

3-4

+1.05V_VCCP
VCC_VCRE

System Reset Circuit

+LCDVCC

Battery Selector & Charger

DDR2_1.8VSUS, 0.9V

1.5VSUS,1.05V(VTT)

VGA DC/DC,1.25V,1.05V

CPU_MAX8786(3phase)

D/D Power

RUN Power Switch

DCIN,Batt

PAD& SCREW

EMI CAP

SMBUS BLOCK

+5V_MOD

Title

QUANTA
COMPUTER
Index, DNI, Power & Ground

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet

3
8

POWER STATES
Signal
State

S0 (Full ON)

SLP
S3#

SLP
S5#

HIGH

ALWAYS
PLANE

SUS
PLANE

RUN
PLANE

CLOCKS

USB PORT#

DESTINATION

Side Pair Top

Side Pair Bottom

Rear Bottom as viewed from the back

Rear Top as viewed from the back

Floppy Disk

S3 (Suspend to RAM)

LOW

HIGH

OFF

S4 (Suspend to DISK)

LOW

HIGH

OFF

S5 (SOFT OFF)

LOW

OFF

SB600

PM TABLE

Dock
C

+3.3V_RUN
power
plane

+2.5V_RUN
+15V_ALW

+5V_SUS

+1.8V_RUN

+5V_ALW

+3.3V_SUS

+1.2V_RUN

+3.3V_ALW

+1.8V_SUS

+1.5V_RUN

+1.2V_ALW_SUS

+0.9V_DDR_VTT

ECE5018

+VCC_CORE
+NB_CORE

State

OFF

S5 S4/AC

OFF

S5 S4 on Battery

OFF

PCI TABLE
REQ#/GNT#

PCI EXPRESS

Cardbus

+5V_RUN

PCI DEVICE

IDSEL

PIRQ

CardBus

AD17

REQ#1/GNT#1 IRQ_SERIRQ
IRQD

Docking

AD24

REQ#0/GNT#0

DESTINATION

Lane 0

MINI CARD-1 WWAN

Lane 1

MINI CARD-2 WLAN

Lane 2

LOM

Lane 3

None

PIRQA

Title

QUANTA
COMPUTER
ATHLON64 HT I/F

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet
1

ADAPTER

RUN_ON

+PWR_SRC

FDS4435BZ

+INV_PWR_SRC

+5V_HDD +5V_MOD +5V_RUN

+VDDA

DDR_ON

+NB_CORE +1.8V_SUS +0.9V_DDR_VTT

+1.2V_RUN
+3.3V_RUN +3.3V_LAN +3VSUS
5755M

FDC655BN

1.5V_RUN_ON

FDC655BN
1.8V_RUN_ON

FDS6670AS

+1.8V_RUN

MAX8794

+1.5V_RUN

REGCTL_PNP12

+5V_SUS

PBSS5540Z
( Q40 )

EMC4001

MBT35200MT1G
( Q39)
L?
(Option)

+1.2V_LOM

REGCTL_PNP25

+2.5V_LOM

+2.5VRUN
Title

DDR_ON

FDS8880

FDC655BN

SUS_ON

AUDIO_AVDD_ENABLE

793475

RUN_ON

MODC_EN#

HDDC_EN#

SI4810

Si4336DY

MAX8632

ISL6236

+1.2V_ALW_SUS

+VCC_CORE

SUS_ON

ENAB_3VLAN

+3.3V_ALW

3.3V_RUN_ON

+5V_ALW

FDC655BN

CPU_VCORE_ENABLE

ALW_ON

MAX8731
Charger

FDC655BN

MAX8774

+15V_ALW

NB_VCORE_RUN_ON

+5V_ALW2

+5V_ALW

1.2V_RUN_ON

ALW_ON

ISL6236

1.2V_ALW_SUS_ON

BATTERY

QUANTA
COMPUTER
ATHLON64 HT I/F

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet
1

SMBUS Address [C8]

+3.3V_SUS
2.2K

SB600

SB_SMBCLK

SB_SMBDATA

5755M
LOM

2.2K

2N7002

MEM_SCLK

197

2N7002

MEM_SDATA

195

+3.3V_SUS

DIMM0
A

SMBUS Address [A0]

+3.3V_WLAN

+3.3V_ALW

197
2.2K

8.2K

+3.3V_RUN

2.2K

LCD_SMBCLK

LCD_SMBDAT +3.3V_ALW

+3.3V_ALW

DIMM1

195

8.2K

SMBUS Address [A2]

SMBUS Address [58]

INV

2N7002

WLAN_SMBCLK 30

2N7002

WLAN_SMBDATA 32

+3.3V_RUN

Inverter

WLAN

SMBUS Address [TBD]

2.2K
B

2.2K

2N7002

CLK_SCLK

2N7002

CLK_SDATA

CKG_SMBCLK

CKG_SMBDAT +3.3V_ALW
+5V_ALW
8.2K

SIO

2.2K

DOCK_SMB_CLK

DOCK_SMB_DAT

SMBUS Address [D2]

CLK GEN.

8.2K
39

+5V_ALW

SMBUS Address [C4, 72, 70, 48]

DOCKING

+3.3V_ALW

2.2K

Macallan IV

2.2K
C

SBAT_DH_SMBCLK

SBAT_DH_SMBDAT

100

+3.3V_ALW

+3.3V_ALW
2.2K
112

PBAT_SMBCLK

111

PBAT_SMBDAT

2'nd
BATTERY

SMBUS Address [16]

BATTERY
CONN

SMBUS Address [16]

100

2.2K
100
100

+3.3V_ALW

3
4

+3.3V_SUS

+3.3V_ALW

CHARGER

4.7K
100

THERM_SMBCLK

THERM_SMBDAT

4.7K

SMBUS Address [12]

9 10
2N7002

+3.3V_ALW
2N7002

2.2K

EMC_SMBCLK

EMC_SMBDATA

GUARDIAN
SMBUS Address [2F]
6

Title

QUANTA
COMPUTER
SMBUS BLOCK

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet

6
8

33 ohm +-25%@100MHz
25m ohm max DC resistance
3A current rating
+3.3V_CLK

L27

0.1U_10V

C174

C137
0.1U_10V

0.1U_10V

C129

0.1U_10V

C169

0.1U_10V

C166

22U_6.3V_0805

C133

C125

C179

220 ohm @100MHz

300mA current rating

0.1U_10V

C599
10U
10
X5R
EP
0805
20

+3.3V_CLK(40 mils)

1
2
BLM18PG330SN1B
0603

+3.3V_RUN

L66

+3.3V_CLK_VDDA

+3.3V_CLK

1
2

CLK_SIO_14M 38
CLK_NB_14M 14
CLK_SB_14M 24
CLK_HTREF_66M 14

1
2

CLK_SB_48M 24

33
33
33
33

49.9_F

R514
R511
R117
R523

49.9_F

FS1
FS0
FS2
HTREFCLK

R534

63
64
62
59

49.9_F

FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0

R537

49.9_F

R526

R541

CLK_SB

R545

7
6

49.9_F

48MHz_1
48MHz_0

49.9_F

LOM_CLKREQ# 30
MINI2CLK_REQ# 35
MINI1CLK_REQ#

CLK_PCIE_SB 23
CLK_PCIE_SB# 23

33
33
R540

R529
R531

49.9_F

PCIE_SB
PCIE_SB#

CLK_NB_SBLINK 14
CLK_NB_SBLINK# 14
CLK_PCIE_MINI2 35
CLK_PCIE_MINI2# 35

R544

Place R535 less than

100mils from Clock Gen.

33
33
33
33

49.9_F

R535
475_F

R539
R543
R547
R549

R548

IREF

NB_SBLINK
NB_SBLINK#
PCIE_MINI2
PCIE_MINI2#

R550

49.9_F

CLKIREF

CLKREQA#
CLKREQB#
CLKREQC#

LOM_CLKREQ#

CLK_PCIE_LOM 30
CLK_PCIE_LOM# 30
CLK_NB_GFX 14
CLK_NB_GFX# 14

49.9_F

SMBCLK
SMBDAT

57
32
33

33
33
33
33

R530

9
10

R533
R536
R542
R546

R532

CLK_SCLK
CLK_SDATA

PCIE_LOM
PCIE_LOM#
NB_GFX
NB_GFX#

CPU_CLK 10
CPU_CLK# 10

RESET_IN#
NC

16
17
41
40
37
36
35
34
30
31
18
19
20
21
24
25
26
27
47
46
43
42
12
13

2 261_F

11
61

39 CLOCK_ENABLE#

SRCCLKT6
SRCCLKC6
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT7
SRCCLKC7

R527 1
2 47.5_F
2 47.5_F

XOUT

R525 1
R528 1

CPUCLK_R
CPUCLK_R#

XIN

56
55
52
51

2 0 XTALOUT_CLK

R520 1

CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1

XTALIN_CLK

GND_CPU
GND_SRC1
GND_SRC2
GND_SRC3
GND_SRC4
GND_48
GND_ATIG
GND_REF
GNDHTT

50
49

R516
1M_NC

53
15
22
29
45
8
38
1
58

VDDA
GNDA

33P
50
NPO

C586
0.047U
16
10
0603
X7R

VDDCPU
VDD_SRC1
VDD_SRC2
VDD_SRC3
VDD_SRC4
VDD_48
VDD_ATIG
VDD_REF
VDDHTT

C584

Y5
14.318MHZ
20PPM
20p
XTALOUT_CLK_C

1
2

33P
50
NPO

C588
B

Parallel Resonance Crystal

C585
2.2U
6.3
0603
X5R

+3VS_CLK_VDDREF

1
2
BLM15AG221SN1D

54
14
23
28
44
5
39
2
60

C603
22U
0805
6.3

+3VS_CLK_VDD48

L67

C128
0.047U
16
10
0603
X7R

+3.3V_RUN

U33
C591
2.2U
6.3
0603
X5R

C602
0.1U
0402
10

L28
1
2
BLM15AG221SN1D

+3.3V_RUN

C172
0.047U
16
10
0603
X7R

BLM15AG221SN1D
1

+3.3V_RUN

ICS951462

R522

+3.3V_RUN

+3.3V_ALW

+3.3V_RUN

+3.3V_ALW

G 2
1 S
2N7002W-7-F

CPU

Hi-Z

100.00

Hi-Z

48.00

Reserved

100.00

X/3

X/6

48.00

Reserved

180.00

100.00

60.00

30.00

48.00

Reserved

220.00

100.00

36.56

73.12

48.00

Reserved

2N7002W-7-F

100.00

66.66

33.33

48.00

Reserved

R517
1

133.33

100.00

66.66

33.33

48.00

Reserved

200.00

100.00

66.66

33.33

48.00

Normal ATHLON64 operation

2
1
2
R509

R116

2.2K_NC

SRCCLK HTT
[2:1]

USB

COMMENT

R519
2.2K

Q64
1

2
1

PCI

FS2 FS1 FS0

1
39 CKG_SMBCLK

R513

EXT CLK FREQUENCY SELECT TABLE(MHZ)

+3.3V_RUN

R524
2.2K

D
3

0_NC
2

2N7002W-7-F
R555
1

2.2K

C596
10P_NC
50V

2 8.2K
2 8.2K
2 8.2K

R113

2.2K

C587
10P_NC
50V

R518 1
R515 1
R114 1

R510

2.2K

FS0
FS1
FS2

R512

C580
10P_NC
50V

1
C127
10P_NC
50V

C589
10P_NC
50V

CLK_SDATA

MINI2CLK_REQ#

CLK_SB_48M
CLK_SIO_14M
CLK_NB_14M
CLK_SB_14M
CLK_HTREF_66M

MINI1CLK_REQ#

Q65
1

39 CKG_SMBDAT

LOM_CLKREQ#
R553
2.2K

R554
2.2K

10K
2
10K
2
10K
2

These are for

backdrive issue.

R507
1
R551
1
R552
1

+3.3V_RUN
2

SMbus address D2

49.9_F

CLK_SCLK

0_NC
2

Title

QUANTA
COMPUTER
CLOCK GENERATOR

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
3A
Sheet

7
8

C512
0.22U
10
0603
X7R

C93
180P_50V

C95
0.22U
10
0603
X7R

C501
4.7U
10
0805
X7R

C502
4.7U
10
0805
X7R

C101
4.7U
10
0805
X7R

+1.2V_RUN

C518
180P_50V

LAYOUT: Place bypass cap on topside of board

NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS

PROCESSOR HYPERTRANSPORT INTERFACE

VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

+1.2V_RUN
C

+1.2V_RUN

R472 1
R473 1

VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

HT_CADOUT15 12
HT_CADOUT#15 12
HT_CADOUT14 12
HT_CADOUT#14 12
HT_CADOUT13 12
HT_CADOUT#13 12
HT_CADOUT12 12
HT_CADOUT#12 12
HT_CADOUT11 12
HT_CADOUT#11 12
HT_CADOUT10 12
HT_CADOUT#10 12
HT_CADOUT9 12
HT_CADOUT#9 12
HT_CADOUT8 12
HT_CADOUT#8 12
HT_CADOUT7 12
HT_CADOUT#7 12
HT_CADOUT6 12
HT_CADOUT#6 12
HT_CADOUT5 12
HT_CADOUT#5 12
HT_CADOUT4 12
HT_CADOUT#4 12
HT_CADOUT3 12
HT_CADOUT#3 12
HT_CADOUT2 12
HT_CADOUT#2 12
HT_CADOUT1 12
HT_CADOUT#1 12
HT_CADOUT0 12
HT_CADOUT#0 12
HT_CLKOUT1 12
HT_CLKOUT#1 12
HT_CLKOUT0 12
HT_CLKOUT#0 12

HT_CADIN15
HT_CADIN#15
HT_CADIN14
HT_CADIN#14
HT_CADIN13
HT_CADIN#13
HT_CADIN12
HT_CADIN#12
HT_CADIN11
HT_CADIN#11
HT_CADIN10
HT_CADIN#10
HT_CADIN9
HT_CADIN#9
HT_CADIN8
HT_CADIN#8
HT_CADIN7
HT_CADIN#7
HT_CADIN6
HT_CADIN#6
HT_CADIN5
HT_CADIN#5
HT_CADIN4
HT_CADIN#4
HT_CADIN3
HT_CADIN#3
HT_CADIN2
HT_CADIN#2
HT_CADIN1
HT_CADIN#1
HT_CADIN0
HT_CADIN#0

N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

12
12
12
12

HT_CLKIN1
HT_CLKIN#1
HT_CLKIN0
HT_CLKIN#0

J5
K5
J3
J2

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

Y4
Y3
Y1
W1

P3
P4

L0_CTLIN_H1
L0_CTLIN_L1

L0_CTLOUT_H1
L0_CTLOUT_L1

T5
R5

N1
P1

L0_CTLIN_H0
L0_CTLIN_L0

L0_CTLOUT_H0
L0_CTLOUT_L0

R2
R3

2 51
2 51

HT_CTLIN1
HT_CTLIN#1

Place R472 and R473 less

than 100mils from CPU

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

AE5
AE4
AE3
AE2

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12 HT_CTLIN0
12 HT_CTLIN#0

+1.2V_RUN

U7A
D4
D3
D2
D1

HT_CPU_CTLOUT1
HT_CPU_CTLOUT#1

T97
T99

Place T97 and T99 less

than 100mils from CPU

HT_CTLOUT0 12
HT_CTLOUT#0 12
Title

Athlon 64 S1
Processor Socket

QUANTA
COMPUTER

ATHLON64 HT I/F

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet
1

+1.8V_SUS

Processor DDR2 Memory Interface

R508
1K_F_0603

0.1U_10V

1
2

2
1

C583

C582

1
R505

U7C

+V_DDR_VREF
17 DDR_B_D[0..63]

2
0_0603_NC

R506
1K_F_0603

1000p_50V

0.1U_10V

for +0.9V_DDR_VTT
feedback

C581

+0.9V_CPU_M_VREF_SUS

CPU_VTT_SUS_SENSE
should be routed as 10mils
and 10mils spacing from any
adjacent signals in X, Y, Z
directions.

Place Capacitors for +0.9V_CPU_M_VREF_SUS < 1" from the RS690.

+0.9V_CPU_M_VREF_SUS trace length < 6", trace width > 15mils and
20mils spacing from any adjacent signals in X, Y, Z directions.

+1.8V_SUS

R95
39.2
1%

CPU_VTT_SUS_SENSE
T113
M_ZN
M_ZP

R100
39.2
1%

VTT_SENSE
MEMZN
MEMZP

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

17,18
17,18
17,18
17,18

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

V19
J22
V22
T19

MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0

MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1

Y16
AA16
E16
F16

M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR0
M_CLK_DDR#0

17
17
17
17

17,18
17,18
17,18
17,18

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

Y26
J24
W24
U23

MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0

MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1

AF18
AF17
A17
A18

M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR2
M_CLK_DDR#2

17
17
17
17

H26
J23
J20
J21

MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

W23
W26
V20
U19

M_ODT3
M_ODT2
M_ODT1
M_ODT0

K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21

MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

17,18 DDR_A_BS2
17,18 DDR_A_BS1
17,18 DDR_A_BS0

K22
R20
T22

MA_BANK2
MA_BANK1
MA_BANK0

MB_BANK2
MB_BANK1
MB_BANK0

K26
T26
U26

DDR_B_BS2 17,18
DDR_B_BS1 17,18
DDR_B_BS0 17,18

17,18 DDR_A_RAS#
17,18 DDR_A_CAS#
17,18 DDR_A_WE#

T20
U20
U21

MA_RAS_L
MA_CAS_L
MA_WE_L

MB_RAS_L
MB_CAS_L
MB_WE_L

U24
V26
U22

DDR_B_RAS# 17,18
DDR_B_CAS# 17,18
DDR_B_WE# 17,18

KEEP TRACE TO RESISTORS LESS

THAN 1.5" FROM CPU PIN
17,18 DDR_CKE3_DIMMB
3

Y10
AE10
AF10

+0.9V_DDR_VTT

MEMVREF

17,18 DDR_CKE2_DIMMB
17,18 DDR_CKE1_DIMMA
17,18 DDR_CKE0_DIMMA
17,18 DDR_A_MA[0..15]

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

17,18
17,18
17,18
17,18

DDR_B_MA[0..15]

To SODIMM socket B (Near/TOP)

U7B

W17

17,18

DDR II: CMD/CTRL/CLK

Athlon 64 S1
Processor Socket
2

17 DDR_B_DM[0..7]

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0
DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

17 DDR_B_DQS[0..7]

17 DDR_B_DQS#[0..7]

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

AD12
AC16
AE22
AB26
E25
A22
B16
A12

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

Y13
AB16
Y19
AC24
F24
E19
C15
E12

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR: DATA

Athlon 64 S1
Processor Socket
17 DDR_A_DQS[0..7]

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

To SODIMM socket A (Far/Bottom)

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER

SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

Notes for the SODIMM locations:

DIMMA = Far = Bottom
DIMMB = Near = Top

17 DDR_A_DQS#[0..7]

Title

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

QUANTA
COMPUTER
ATHLON64 DDRII MEMORY

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet
E

SB600 ONLY
CPU_PWRGD

23 CPU_PWRGD

R498 1

LDT_STOP_R#

2 0_NC

R85
680
+1.8V_RUN

+1.8V_SUS

R666
0_NC
D

R667
0
D

D31

LAYOUT: ROUTE VDDA TRACE APPROX.

+2.5V_CPU_VDDA_RUN
C526
4.7U
10
0805
X7R

If AMD SI is not used, the SID pin can be left unconnected

and SIC should have a 300- (5%) pulldown to VSS.

C525
0.22U
10
0603
X7R

To Power

NOTE: Place R88 on the top of the board that is

iaccessible, and that shorting across this
resistor will toggle the hyper Transport reset
signal.

R88
680
C

C115 1

The AMD SI feature has errata, and will not be plemented.

R80
R81

R78
R77

1
1

2 300
2 0_NC

1
1

CPU_SIC AF4
CPU_SID AF5

CPU_HTREF1
CPU_HTREF0

2 44.2_F
2 44.2_F
T103
T105

CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L

VDDA2
VDDA1

VID5
VID4
VID3
VID2
VID1
VID0

SIC
SID
HT_REF1
HT_REF0

F6
E6

VDD_FB_H
VDD_FB_L

A9
A8

THERMTRIP_L
PROCHOT_L

RESET_L
PWROK
LDTSTOP_L

P6
R6

W9
Y9

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
CPU_CLK
CPU_CLK#
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

2 3900P_50V

B7
A7
F10

CPU_PRESENT_L
PSI_L

G10

DBRDY

AA9
AC9
AD9
AF9

TMS
TCK
TRST_L
TDI

E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12

C3
AA6
W7
W8
Y6
AB6

TEST7
TEST6
TEST5
TEST4
TEST3
TEST2

P20
P19
N20
N19

RSVD0
RSVD1
RSVD2
RSVD3

A5
C6
A6
A4
C5
B5
AC6

VID5
VID4
VID3
VID2
VID1
VID0

50
50
50
50
50
50

CPU_PRESENT#

CPU_PSI# 50

PSI_L is a Power Status Indicator signal. This signal is asserted when the
processor is in a low powerstate. PSI_L should be connected to the power
supply controller, if the controller supports skipmode, or diode emulation
mode. PSI_L is asserted by the processor during the C3 and S1 states.

CLKIN_H
CLKIN_L

CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

H_THERMTRIP# 19

T24

VDDIO_FB_H
VDDIO_FB_L

CPU_DBRDY

AF6 H_THERMTRIP#
AC7 CPU_PROCHOT#

R478
300

DBREQ_L

E10

CPU_DBREQ#

TDO

AE9

CPU_TDO

CPU_CLK

F8
F9
LDT_RST#
CPU_PWRGD
LDT_STOP_R#

50 CPU_VDD_RUN_FB_H
50 CPU_VDD_RUN_FB_L

T117
T114
T31
T32
T115
T111

U7D

LDT_RST#

R486
300

C536
3300P
50
5
LF (Lead Free)
0402
X7R

+1.2V_RUN

Place R78 and R77 < 1.5".

Route CPU_HTREF1/0 with 5mils trace width and 10mils
spacing from other signals in X, Y, Z directions

+2.5V_CPU_VDDA_RUN

NOTE: R499 and C564 close to

JCPU pin F10

L65 0603
2
1
BLM18PG330SN1D
C130
+ 100U
6.3
3528
Polymer
20

+1.8V_SUS

+2.5V_RUN

+2.5V_CPU_VDDA_RUN

NL17SZ17DFT2G

EXIT BALL FIELD) AND 500 mils LONG.

This trace should be kept at least 20 mils away from all other signals.

R669
680_NC

L65 ferrite bead with an approximate

impedance of 33 , a maximum DC
resistance of 0.025 ohm , and a current
rating of at least 3000mA.

C760
47P
NPO
50

C564
0.1U_16V_NC

U35

1
2

R499
680

20K
1%

50 mils WIDE (USE 2x25 mil TRACES TO

R668

14,23 LDT_STOP#

SDMK0340L-7-F

R91
169_F
2 3900P_50V

C111 1

+1.8V_SUS

1.KEEP TRACE TO RESISTOR LESS THAN 600MILS FROM CPU

PIN AND TRACE TO AC CAPS LESS THAN 1250MILS.
2. CPUCLK and CPUCLK# mismatch < 35 mils.

+1.8V_SUS
+3.3V_SUS

R479
4.7K

CPU_PROCHOT#

Q61
1

2 1

R485
10K

EC_CPU_PROCHOT#

CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H

R90 1
R86 1
R477 1
R497

2 300_NC
2 300
2 1K_F
510 1%

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0

R491
R84
R87
R92
R487
R480
R481

2
2
2
2
2
2
2

CPU_TEST25_L_BYPASSCLK_L

R484

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

R482 1
R483 1

If no use which Net

need pull-up or down

1
1
1
1
1
1
1

T25
T108
T102
T104
T106

300
300_NC
300_NC
300_NC
300_NC
300_NC
300_NC

H_THERMDC

H_THERMDA

C531
220P
50V

H_THERMDC
H_THERMDA

Place C32< 100mils from CPU.

T134
T124
T129
T128

510 1%
2 300
2 300

CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB

CPU_CLK#

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

T119
T110
T118
T116

CPU_RSVD_MA0_CLK3_P
CPU_RSVD_MA0_CLK3_N
CPU_RSVD_MA0_CLK0_P
CPU_RSVD_MA0_CLK0_N

MMBT3904

MISC

T130
T131
T122
T126

CPU_RSVD_MB0_CLK3_P
CPU_RSVD_MB0_CLK3_N
CPU_RSVD_MB0_CLK0_P
CPU_RSVD_MB0_CLK0_N

R26
R25
P22
R22

RSVD4
RSVD5
RSVD6
RSVD7

220_NC
220_NC
220_NC
220_NC
220_NC

+1.8V_SUS

1
1
1
1
1

HDT conn_NC

+3.3V_RUN

+1.8V_RUN

TEST24
TEST23
TEST22
TEST21
TEST20

AE7
AD7
AE8
AB8
AF7

CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2

TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8

J7
H8
AF8
AE6
K8
C4

CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#

RSVD8
RSVD9

H16
B18

CPU_MA_RESET#
CPU_MB_RESET#

RSVD10
RSVD11

B3
C1

CPU_RSVD_VIDSTRB1
CPU_RSVD_VIDSTRB0

RSVD12
RSVD13
RSVD14

H6
G6
D5

CPU_RSVD_VDDNB_FB_P
CPU_RSVD_VDDNB_FB_N
CPU_RSVD_CORE_TYPE

R24
W18
R23
AA8
H18
H19

CPU_RSVD_15
CPU_RSVD_16
CPU_RSVD_17
CPU_RSVD_18
CPU_RSVD_19
CPU_RSVD_20

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

1 80.6_F

T29
T109
T30
T112
T27

T28
T26

T120
T123
T22
T23
T98
T100
T101
T133
T121
T132
T107
T125
T127

1
R67
4.7K
2 2

R64
4.7K
2

R98
R101
R494
R492
R493

+1.8V_SUS

2
4
6
8
10
12
14
16
18
20
22
24
25

R490 2

ROUTE AS 80 Ohm DIFFERENTIAL PAIR

PLACE IT CLOSE TO CPU WITHIN 1"

Q13
3
1 LDT_RST#
MMBT3904

CPU_RESET#

NOTE:HDT TERMINATION IS REQUIRED FOR REV.Ax SILICON ONLY.

R66
100K_NC
2

GND
GND
Resreved1
GND
Resreved2
GND
DBREQ_L
GND
DBRDY
GND
TCK
GND
TMS
GND
TDI
GND
TRST_L
GND
TDO
GND
VDDIO1
GND
VDDIO2
RESET_L
GND

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

2
2
2
2
2

JHDT1
1
3
5
7
9
11
13
15
17
19
21
23

C9
C8

AMD NPT S1 SOCKET

Processor Socket

HDT CONNECTOR

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

TEST29_H
TEST29_L

Title

QUANTA
COMPUTER
ATHLON64 CTRL & DEBUG

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
3A
Sheet
1

C549
22U
6.3
0805
X6S

C550
22U
6.3
0805
X6S

C530
22U
6.3
0805
X6S

C538
22U
6.3
0805
X6S

1
2

0.01U_16V

C535

C558
180P_50V

C528
0.22U
10
0603

C560
0.22U
10
0603

1
2

C554
22U
6.3
0805
X6S

C576
0.22U
10
0603

C571
0.22U
10
0603

1
2

C569
22U
6.3
0805
X6S

C545
22U
6.3
0805
X6S

C543
22U_NC
6.3
0805
X6S

22uF/0805/6.3V/X6S
0.22uF/0603/10V/X7R
0.01uF/0402/16V/X7R
180pF/0402/50V/NPO

C567
22U_NC
6.3
0805
X6S

DECOUPLING BETWEEN PROCESSOR AND DIMMs

PLACE CLOSE TO PROCESSOR AS POSSIBLE

C184
10U
10
0805
X7R

C187
10U
10
0805
X7R

C186
10U
10
0805
X7R

+1.8V_SUS

C185
10U
10
0805
X7R

C601
0.22U
10
0603
X7R

C593
0.22U
10
0603
X7R

C600
0.22U
10
0603
X7R

C592
0.22U
10
0603
X7R

0.01U_16V

180P_50V

C568

C597
180P_50V

0.01U_16V

C595

C594

+1.8V_SUS

C568 to be
placed as close
as possible to
the socket
C597,and C598 to be
evenly spaced along the
180P_50V VDDIO/VSS plane split
C598

22uF/0805/6.3V/X6S
10uF/0805/10V/X7R
4.7uF/0805/10V/X7R
0.22uF/0603/10V/X7R
0.01uF/0402/16V/X7R
1000pF/0402/50V/X7R
180pF/0402/50V/NPO

A26

C540
4.7U
10
0805
X7R

C552
4.7U
10
0805
X7R

C117
4.7U
10
0805
X7R

+0.9V_DDR_VTT

GROUND

Athlon 64 S1
Processor Socket

C566
22U
6.3
0805
X6S

C557
22U
6.3
0805
X6S

POWER

Athlon 64 S1
Processor Socket

C529
22U
6.3
0805
X6S

+1.8V_SUS

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

+1.8V_SUS

C539
22U
6.3
0805
X6S

+VCC_CORE

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AC4
AD2
G4
H2
J9
J11
J13
K6
K10
K12
K14
L4
L7
L9
L11
L13
M2
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10

AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4

+VCC_CORE

U7E

U7F
+VCC_CORE

BOTTOMSIDE DECOUPLING

+VCC_CORE

C121
4.7U
10
0805
X7R

C565
0.22U
10
0603
X7R

C544
0.22U
10
0603
X7R

C551
0.22U
10
0603
X7R

C555
0.22U
10
0603
X7R

180P_50V

C562
180P_50V

C553

180P_50V

C119

1000p_50V

C556

1000p_50V

C120

1000p_50V

C546

1000p_50V

C118

uPGA638

Athlon 64 S1g1

+0.9V_DDR_VTT

C122
180P_50V

Top View

AF1

PROCESSOR POWER AND GROUND

Title

QUANTA
COMPUTER
ATHLON64 PWR & GND

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
1A
Sheet
1

Change Part Number

U5A
HT_CADOUT15
HT_CADOUT#15
HT_CADOUT14
HT_CADOUT#14
HT_CADOUT13
HT_CADOUT#13
HT_CADOUT12
HT_CADOUT#12
HT_CADOUT11
HT_CADOUT#11
HT_CADOUT10
HT_CADOUT#10
HT_CADOUT9
HT_CADOUT#9
HT_CADOUT8
HT_CADOUT#8

R19
R18
R21
R22
U22
U21
U18
U19
W19
W20
AC21
AB22
AB20
AA20
AA19
Y19

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

HT_CADOUT7
HT_CADOUT#7
HT_CADOUT6
HT_CADOUT#6
HT_CADOUT5
HT_CADOUT#5
HT_CADOUT4
HT_CADOUT#4
HT_CADOUT3
HT_CADOUT#3
HT_CADOUT2
HT_CADOUT#2
HT_CADOUT1
HT_CADOUT#1
HT_CADOUT0
HT_CADOUT#0

T24
R25
U25
U24
V23
U23
V24
V25
AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

8 HT_CLKOUT1
8 HT_CLKOUT#1

W21
W22

HT_RXCLK1P
HT_RXCLK1N

8 HT_CLKOUT0
8 HT_CLKOUT#0

Y24
W25

HT_RXCLK0P
HT_RXCLK0N

8 HT_CTLOUT0
8 HT_CTLOUT#0

P24
P25

HT_RXCTLP
HT_RXCTLN

A24
C24

HT_RXCALP
HT_RXCALN

R429 1
R453 1

2 49.9_F HT_RXCALP
2 49.9_F HT_RXCALN

+VDDHT_PKG

PART 1 OF 6

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

HT_CADIN15 8
HT_CADIN#15 8
HT_CADIN14 8
HT_CADIN#14 8
HT_CADIN13 8
HT_CADIN#13 8
HT_CADIN12 8
HT_CADIN#12 8
HT_CADIN11 8
HT_CADIN#11 8
HT_CADIN10 8
HT_CADIN#10 8
HT_CADIN9 8
HT_CADIN#9 8
HT_CADIN8 8
HT_CADIN#8 8

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25

HT_CADIN7
HT_CADIN#7
HT_CADIN6
HT_CADIN#6
HT_CADIN5
HT_CADIN#5
HT_CADIN4
HT_CADIN#4
HT_CADIN3
HT_CADIN#3
HT_CADIN2
HT_CADIN#2
HT_CADIN1
HT_CADIN#1
HT_CADIN0
HT_CADIN#0

HT_TXCLK1P
HT_TXCLK1N

L21
L22

HT_CLKIN1 8
HT_CLKIN#1 8

HT_TXCLK0P
HT_TXCLK0N

J24
J25

HT_CLKIN0 8
HT_CLKIN#0 8

HT_TXCTLP
HT_TXCTLN

N23
P23

HT_CTLIN0 8
HT_CTLIN#0 8

HT_TXCALP
HT_TXCALN

C25 HT_TXCALP
D24 HT_TXCALN

HYPER TRANSPORT CPU I/F

8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

RS690T

R450 1

8
8
8
8
8
8
8
8

2 100_F

Place R450 < 100 mils from U5A.C25 and U5A.D24

Rev.A12

check

Title

QUANTA
COMPUTER

RS690T-HT LINK0 I/F

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
2A
Sheet
1

DVI_TX2+
DVI_TX2DVI_TX1+
DVI_TX1DVI_TX0+
DVI_TX0DVI_CLK+
DVI_CLK-

U5B

WLAN <----GIGA LAN <-----

35 PCIE_NBRX_WLANTX_P1
35 PCIE_NBRX_WLANTX_N1

G5
G4
J8
J7
J4
J5
L8
L7
L4
L5
M8
M7
M4
M5
P8
P7

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N

R7
R8
U4
U5
P4
P5

30 PCIE_NBRX_LOMTX_P2
30 PCIE_NBRX_LOMTX_N2

R4
R5

23
23
23
23
23
23
23
23

ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3

DVI_C_TX2+
DVI_C_TX2DVI_C_TX1+
DVI_C_TX1DVI_C_TX0+
DVI_C_TX0DVI_C_CLK+
DVI_C_CLK-

C72
C71
C80
C75
C73
C74
C81
C82

0.1U_16V
0.1U_16V
0.1U_16V
0.1U_16V
0.1U_16V
0.1U_16V
0.1U_16V
0.1U_16V

DVI_TX2+
DVI_TX2DVI_TX1+
DVI_TX1DVI_TX0+
DVI_TX0DVI_CLK+
DVI_CLK-

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N

J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2

GPP_RX0P
GPP_RX0N

GPP_TX0P
GPP_TX0N

V3
W3

GPP_RX1P
GPP_RX1N

GPP_TX1P
GPP_TX1N

W1
W2

PCIE_NBTX_WLANRX_P1
PCIE_NBTX_WLANRX_N1

C85

0.1U 10
X7R C86

GPP_TX2P
GPP_TX2N

U2
U1

PCIE_NBTX_LOMRX_P2
PCIE_NBTX_LOMRX_N2

C83

0.1U 10
X7R C84

GPP_TX3P
GPP_TX3N

V2
V1

GPP_RX2P
GPP_RX2N

PCIE I/F
GFX

PCIE I/F GPP

GPP_RX3P
GPP_RX3N

AB7
AB6
V9
W9
Y4
Y5
W4
W5

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

AC4
AD4

NC_1
NC_2

RS690T

PCIE I/F SB

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
PCE_PCAL
PCE_NCAL

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

36
36
36
36
36
36
36
36

No placement limitation,
minimum stub

Place near RS690T

PART 2 OF 6

DVI_TX2+
DVI_TX2DVI_TX1+
DVI_TX1DVI_TX0+
DVI_TX0DVI_CLK+
DVI_CLK-

R454
R452
R465
R460
R73
R74
R75
R76

750
750
750
750
750
750
750
750

1%
1%
1%
1%
1%
1%
1%
1%

Layout Note :750 ohm

resistors
are placed at the same
via as
the series capacitors

ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3

AC1
AC2
AB1
AB2
AA1
AA2
Y2
Y3

AE4 PCE_PCAL
AE3 PCE_NCAL

R83
R82

1
1

C94

0.1U
X7R
0.1U
X7R
0.1U
X7R
0.1U
X7R

C91
C89
C87

562_F
2 2K_F

10
C96
10
C92
10
C90
10
C88

0.1U
X7R

PCIE_NBTX_C_WLANRX_P1 35
PCIE_NBTX_C_WLANRX_N1 35

0.1U
X7R

PCIE_NBTX_C_LOMRX_P2 30
PCIE_NBTX_C_LOMRX_N2 30

0.1U
X7R
0.1U
X7R
0.1U
X7R
0.1U
X7R

ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3

10
10
10

----->WLAN
----->GIGA LAN

23
23
23
23
23
23
23
23

+1.2V_VDDA12

Rev.A12

Title

QUANTA
COMPUTER
RS485-PCIE LINK I/F

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
3A
Sheet
1

+1.8V_RUN
+1.8V_AVDDQ

+3.3V_RUN
L20
+3.3V_AVDD
1
2
BLM18PG330SN1_0603
C57

R444
150
1%

+1.8V_PLLVDD

R451
150
1%

R435
150
1%

2.2U_10V_0603

C453

2
1

10U_10V_0805_NC

L18

C52

TV_CVBS
TV_Y
TV_C

L19
BLM15AG221SN1D

2.2U_10V_0603

BLM15AG221SN1D
+1.8V_RUN_AVDDDI

U5C

2 4.7K

7 CLK_HTREF_66M

2.2U_10V_0603
7 CLK_NB_14M

R433 1
22_NC

R427 1
33 1%

1
50

1 0

19 NB_THERMDC

TMDS_HPD
DDC_DATA

Place C98 < 100mils from RS690T

49 NB_VCORE_CNTRL

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

E15
D15
H15
G15

LCD_ACLK+
LCD_ACLKLCD_BCLK+
LCD_BCLK-

LPVDD
LPVSS

D14
E14

LVDDR18D_1
LVDDR18D_2
LVDDR33A_1
LVDDR33A_2

A12
B12
C12
C13

LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8

A16
A14
D12
C19
C15
C16

LVSSR12
LVSSR13

F14
F15

LVDS_DIGON
LVDS_BLON
LVDS_BLEN

E12
G12
F12

VDDPLL_1(VDDA12)
VDDPLL_2(VDDA12)
VSSPLL_1(VSSA12)
VSSPLL_2(VSSA12)

C10
C11
C5
B5

SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

C23
B23

HTTSTCLK
HTREFCLK
TVCLKIN

+LVDDR18D

GFX_CLKP
GFX_CLKN

G1
G2

SB_CLKP
SB_CLKN

B2
A2
B4
AD5
AE5

BMREQb
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

C14
B3
C3
A3

TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

MIS.

D6
D7
C8
C7
B8
A8

DFT_GPIO0
LOAD_ROM#
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS IS MANDATORY.

R423
R449
R424
R420
R421
R422

1
DVI_SCLK

R57

1 0

1
1
1
1
1
1

2
2
2
2
2
2

3K
3K_NC
3K_NC
3K_NC
3K_NC
3K_NC

DVI_SCLK 21,36

Q11

Title

2
2

1 0_NC

4.7U_6.3V_0603

1
DDC_DATA

R59

C452

PU by internal
PD by external
Side-Port Memory Disable Side-Port Memory Enable
(Default)
Bypassing EEPROM, use
default values
Using EEPROM Strapping
DFT_GPIO1
(Default)
Set PCI-E GPP mode to
Select PCI-E GPP mode
DFT_GPIO[4:2]
Conf. E
Use default values
Use the memory data bus
DFT_GPIO5
for debug bus output
(Default)

2
2
LCD_DDCDAT

C468
0.1U_10V

DFT_GPIO0

R37
4.7K

R46
4.7K
2

R58
4.7K

2.2U_10V_0603

2N7002W-7-F
+5V_RUN

R50
100K

C46
0.01U
X7R
16
0603

Q10
3

+3.3V_RUN
1

1
R456
2K_NC
2

C483
0.1U_NC
16

2
0

2
2

36 DVI_DETECT

C461

EN_LCDVDD 20
BIA_PWM 20
PANEL_BKEN 38

R36
4.7K

0.1U_10V

DFT_GPIO5 22

+5V_RUN

LCD_DDCCLK
R51

C463

Rev.A12

R45
4.7K

TMDS_HPD

BLM15AG221SN1D

R459
100K

+3.3V_RUN

For DVI Hot Plug

L16

BLM15AG221SN1D
C55
+1.8V_RUN
2.2U_10V_0603
L54

+LVDDR33A

OSCIN
PLLVDD12(OSCOUT)

F2
E1

C477
0.1U_10V

+1.8V_RUN
L55
1
2
BLM15AG221SN1D

+LPVDD

+3.3V_RUN
20
20
20
20

HTPVDD
HTPVSS

20
20
20
20
20
20

RS690T

1
R457
2K_NC

LCD_DDCCLK
NB_VCORE_CNTRL

AT24C04N-10SU-2.7_NC

B24
B25

R69
4.7K

8
7
6
5

C98
220P
50V

2
R434

SDMK0340L-7-F_NC

C466
15P_NC

20 LCD_DDCCLK
20 LCD_DDCDAT

19 NB_THERMDA

PLLVDD18(PLLVDD)
PLLVSS

B11
A11

7 CLK_NB_GFX
7 CLK_NB_GFX#

BMREQ#_D

A10
B10

+1.2V_PLLVDD12

2
1

D23

R458
10K_NC
VCC
WP
SCL
SDA

2 10K

BMREQ#_D

U32
NC
A1
A2
VSS

7 CLK_NB_SBLINK
7 CLK_NB_SBLINK#

BMREQ#

1
2
3
4

LDT_STOP#_NB

DACSCL
DACSDA

LCD_B0+
LCD_B0LCD_B1+
LCD_B1LCD_B2+
LCD_B2-

2 C456
22P NPO

+3.3V_RUN

R72

24 SUS_STAT#

R441
10K_NC

2 0
2 0

R70

2 C464
50 22P_NC

AC Term closely clock

pin for length: 50 mils

+3.3V_RUN

R425 1
R431 1

AC Term closely clock

pin for length: 50 mils

1
2

C451

RSET

E7
F7
F9
G9

23 ALLOW_LDTSTOP

BLM15AG221SN1D

B21

A15
B16
C17
C18
B17
A17
A18
B18

C478
1U
10
0603
X6S
+/-10%

22,30,35,43,49 PLTRST_SYS#
20,39 NB_PWRGD

SUS_STAT#

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

B6
A6

21 G_CLK_DDC2
21 G_DAT_DDC2

+1.8V_HTPVDD

4.7U_6.3V_0603

E19
F19
G19
C6
A5

TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

2 1

+1.2V_VDDA12
+1.2V_VDDPLL
L58
1
2
BLM21PG221SN1D
Imax = 2
0805
C485

LDT_STOP#_NB

R71

1 715_F

+1.8V_PLLVDD

+3.3V_RUN

+1.2V_PLLVDD12

R432 2

10K

RS690: 220 Ohm 2A FB

+1.2V_VDDA12
L53

R461
150
1%
0402

CRT_VSYNC
CRT_HSYNC

C_R
Y_G
COMP_B

1
R455
150
1%
0402

R49

Q12
1
3
MMBT3904

10,23 LDT_STOP#

R446
150
1%
0402

2
R47
4.7K

+3.3V_RUN

+1.8V_RUN

21
21

AVDDQ
AVSSQ

C21
C20
D19

20
20
20
20
20
20

VGA_RED
VGA_GRN
VGA_BLU

TV_C
TV_Y
TV_CVBS

LCD_A0+
LCD_A0LCD_A1+
LCD_A1LCD_A2+
LCD_A2-

R446,R455,R461 CLOSE TO NB
21,36
21,36
21,36

4.7U_6.3V_0603

22,36
22,36
22,36

A21
A22

B14
B15
B13
A13
H14
G14
D17
E17

C68
1U
6.3
X5R

10U_10V_0805_NC

C64

C66

BLM15AG221SN1D

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

+1.8V_HTPVDD

L22

PART 3 OF 6

+1.8V_AVDDQ
+1.8V_RUN

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

2.2U_10V_0603

B22
C22
G17
H17
A20
B20

C56

CRT/TVOUT

+1.8V_RUN
R60

PLL PWR

2.2U_10V_0603

CLOCKs PM

R435, R451 and R444

should be placed
close to NB

10U_10V_0805_NC

C54

C53

DVI_SDAT

DVI_SDAT 36

2N7002W-7-F
2

QUANTA
COMPUTER
RS690T-LVDS

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
2A
Sheet
1

+1.2V_RUN

L62
BLM21PG221SN1D_0805

20mil Width

2.2U_10V_0603

1U_6.3V

+1.8V_RUN

1U_6.3V

C517

C514

1U_6.3V

C515

1U_6.3V

C516

1U_6.3V

C521

10U_6.3V_0603

C506

10U_6.3V_0603

1
2

C522

1U_6.3V

C488
0.1U_NC
16V
X5R, 10%

+1.8V_VDD_MEM

80mil Width

L61
1
2
BLM21PG221SN1D_0805

C499

C500

C498
1U
10
0603
X6S

C496
1U
10
0603
X6S

10U_6.3V_0603

1
J14
J15

VDD18_1
VDD18_2

C510
0.1U_NC
16V
X5R, 10%

E11
D11

VDDR3_2
VDDR3_1

AC5
AB3
U7
W7
AB4
AC3
AD2
AE2

VDDA12_13
VDDA12_14
VDDA12_15
VDDA12_16
VDDA12_17
VDDA12_18
VDDA12_19
VDDA12_20

AD6
AC7
AC8
AA9
AD7
AB9
AE6
AE8
AE7
AD8

VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM9
VDD_MEM10
VDD_MEM11

RS690T

C519
10U_6.3V_0603

1U_6.3V

C465

L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15

C479
1U
10
0603
X6S
+/-10%

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
Rev.A12

C490
1U
10
0603
X6S
+/-10%

C524

10U_6.3V_0603

+1.2V_VDDA12
C494

10U X5R
10 0805

C495
10U
20
4
0805
X6S
EP
C471
0.1U
10
X7R

+NB_VCORE

C497
10U
EP
X6S
0805
20
4
C481
0.1U
10
X7R

C486
0.1U
10
X7R

C491
0.1U
10
X7R

C492
0.1U
10
X7R
U5E

C487
0.1U
10
X7R

A25
F11
D23
E9
G11
Y23
P11
R24
AC18
M15
J22
G23
J12
L12
L14
L20
L23
M11
M20
M23
M25
N12
N14
B7
L24
P13
P20
P15
R12
R14
R20
W23
Y25
AD25
U20
H25
W24
Y22
AC23
D25
G24
AA14
H12
AC22
R23
C4
Y12
T23
T25
V11
R17
H23

C493
0.1U
10
X7R

PAR 5 OF 6

GROUND

C467

C523

1
2

10U_6.3V_0603

VDDHT_PKG

1U_10V_0603

40mil Width
C505

D22

100 mil Width

C482
1U
10
0603
X6S
+/-10%

+VDDHT_PKG

D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6
AD3
M1

source
C458

+1.2V_VDDA12

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7

+3.3V_VDDR
1

L57
1
2
BLM15AG221SN1D

+3.3V_RUN

1U_10V_0603

1
2

220 ohm @ 100MHz, 2A

C457

VDDA_12_1
VDDA_12_2
VDDA_12_3
VDDA_12_4
VDDA_12_5
VDDA_12_6
VDDA_12_7
VDDA_12_8
VDDA_12_9
VDDA_12_10
VDDA_12_11
VDDA_12_12
VDDA12_PKG2
VDDA12_PKG1

PART 4 OF 6
AE24
AD24
AE25
AE22
AD22
AE23
AD23

+1.8V_VDD

30mil Width

220 ohm @ 100MHz, 2A

U5D

L52
1
2
BLM21PG221SN1D_0805

C513
0.1U_NC
16V
X5R, 10%

POWER

+1.8V_RUN

C504
0.1U
16
X7R
+/-10%

1U_6.3V

C100

1U_6.3V

C99

C511

1U_6.3V

10U_6.3V_0603

C503

10U_6.3V_0603

C102

C103

+1.2V_VDDA12

VSSA1
VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8
VSSA9
VSSA10
VSSA11
VSSA12
VSSA13
VSSA14
VSSA15
VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22
VSSA23
VSSA24
VSSA25
VSSA26
VSSA27
VSSA28
VSSA29
VSSA30

M3
P9
G6
AE1
F3
AD1
A1
H1
G3
J2
H3
AA3
J6
Y7
F1
L6
M2
M6
J3
P6
T1
N3
R9
R6
T2
T3
U3
U6
W6
Y1

VSS66
VSS65
VSS64
VSS62
VSS63
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53

RS690T

AC12
AC10
V14
W17
AB19
AE18
AE14
M13
AA7
D4
F17
AC6
A23
M17

Rev.A12

Title

QUANTA
COMPUTER
RS690-POWER

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
2A
Sheet
1

L2
L3

BA0
BA1

MEM_DM1
MEM_DM0

B3
F3

UDM
LDM

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
MEM_CLKP

K7
L7
K3
L8
K2
K9

RAS
CAS
WE
CS
CKE
ODT

J8
K8

MEM_CLKN

UDQS
UDQS#

B7
A8

MEM_DQS_P1
MEM_DQS_N1

LDQS
LDQS#

F7
E8

MEM_DQS_P0
MEM_DQS_N0

NC1
NC2
NC3
NC4
NC5
NC6

A2
E2
L1
R3
R7
R8

CLK
CLK#

L63
J1

1
2
BLM18AG601SN1D_0603

+1.8V_MEM_VDDQ

C532
4.7U_6.3V_0603

Place This CAP near to

SDRAM with 0.2".

VDDL

VSSDL

A3
E3
J3
N1
P9

VSS_0
VSS_1
VSS_2
VSS_3
VSS_4

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSSQ_0
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

A1
E1
J9
M9
R1

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

MEM_BA2

MEM_VREF

+1.8V_MEM_VDDQ

PAR 6 OF 6

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

W12
AD10
AB12
AB11
W14
AB15
AB14
AE9
AA12
AC9
AE10
Y14
AD9
AA11

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13

MEM_BA0
MEM_BA1
MEM_BA2

AC11
AE11
AD11

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#

AA15
Y15
AC14
V12

MEM_RASb
MEM_CASb
MEM_WEb
MEM_CSb

MEM_CKE
MEM_ODT

AD12
Y9

MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

W15
V15

MEM_CKP
MEM_CKN

MEM_DM0
MEM_DM1

AC16
AD19

MEM_DM0
MEM_DM1

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

AE17
AD17
AD21
AC20

MEM_DQS0P
MEM_DQS0N
MEM_DQS1P
MEM_DQS1N

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

AD13
AE13
AC13
AD14
AC15
AD15
AE15
AE16
AD16
AC17
AD18
AE19
AC19
AE20
AD20
AE21

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_COMP_P and MEM_COMP_N trace

width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions
+1.8V_MEM_VDDQ
MEM_COMPP
MEM_COMPN
MEM_VREF
IOPLLVDD18
IOPLLVSS
IOPLLVDD12

Y11
W11
AE12
AA17
Y17
AB17

MEM_COMP_P
MEM_COMP_N
MEM_VREF1
+1.8V_IOPLLVDD

R471 1
R474 1

2 40.2_F
2 40.2_F

L59
+1.2V_IOPLLVDD 1
2
BLM15AG221SN1D
C508
2.2U
10
10%
0603
X7R
EP

RS690T

Rev.A12

MEM_A2
MEM_A0
MEM_A6
MEM_A4
MEM_A11
MEM_A8
MEM_A5
MEM_A7
MEM_A3
MEM_A9
MEM_BA2
MEM_A10
MEM_A12
MEM_A1
MEM_BA1
MEM_BA0

256-Mbit DDR2 16Mbit*16(4bank)

Q16
BSC032N03S-G_PG-TDSON-8
+0.9V_DDR_VTT
1
2
3
5

C108
22U_6.3V_0805

100U_6.3V_3528

1
0.1U_10V

C507
2.2U_10V_0603
B

RP15
RP13
RP14
RP9
RP12
RP10
RP8
RP11

1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3

2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4

4P2R-47

C572 2

1 0.1U_10V

4P2R-47

C107 2

1 0.1U_10V

4P2R-47

C561 2

1 0.1U_10V

4P2R-47

C112 2

1 0.1U_10V

4P2R-47

C563 2

1 0.1U_10V

4P2R-47

C534 2

1 0.1U_10V

4P2R-47

C570 2

1 0.1U_10V

4P2R-47

C104 2

1 0.1U_10V

MEM_RAS#
MEM_CAS#
MEM_WE#

R503
1
R502
1
R489
1

2 47
2 47
2 47

C527 2

1 0.1U_10V

C105 2

1 0.1U_10V

MEM_CS#
MEM_CKE
MEM_ODT

R500
1
R488
1
R501
1

2 47
2 47
2 47

C573 2

1 0.1U_10V

C123 2

1 0.1U_10V

+1.8V_MEM_VDDQ

42 1.8V_RUN_ENABLE
MEM_VREF1

MEM_VREF

R496
1K_F

C509

R475
1K_F

0.1U_10V
2

0.1U_10V

C116
R476
1K_F

1
2

C520

2
1

C547

R495
1K_F

0.1U_10V

+0.9V_MEM_VTT

+1.8V_MEM_VDDQ

1
2
1

C548

+1.2V_VDDA12

+0.9V_MEM_VTT

HY5PS561621AFP-25
400M PBGA84
256M EP

+1.8V_MEM_VDDQ

+1.8V_RUN
L60
1
2
BLM15AG221SN1D
1

R504

MEM_BA0
MEM_BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

Place R504 to close

to U5.

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

U5F

MEM_DQ5
MEM_DQ3
MEM_DQ0
MEM_DQ6
MEM_DQ2
MEM_DQ4
MEM_DQ1
MEM_DQ7
MEM_DQ15
MEM_DQ9
MEM_DQ11
MEM_DQ12
MEM_DQ8
MEM_DQ13
MEM_DQ10
MEM_DQ14

G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9

M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2

Bit Swap

U6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

SBD_MEM_I/F

+1.8V_MEM_VDDQ

C537

+
330U_6.3V_ESR25

C559
0.1U_10V

22U_6.3V_0805

C533

1
2
BLM21PG221SN1D_0805

+1.8V_RUN
D

L64
D

C542

Title

Local Frame Buffer(64MB) DDRII Power

QUANTA
COMPUTER

0.1U_10V

RS690T-SIDE PORT I/O

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
3A
Sheet

16
8

+1.8V_SUS

+0.9V_DDR_REF

9,18

DDR_A_CAS#
M_ODT1

M_ODT1

DDR_A_D36
DDR_A_D33
2

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D35
DDR_A_D34
DDR_A_D45
DDR_A_D44
DDR_A_DM5
DDR_A_D43
DDR_A_D47
DDR_A_D49
DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D61
DDR_A_DM7

DDR_A_D58
DDR_A_D59
MEM_SDATA
MEM_SCLK

C283
0.1U_10V

DDR_A_D28
DDR_A_D24

DDR_B_D25
DDR_B_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_B_DM3

DDR_A_D26
DDR_A_D31

DDR_B_D26
DDR_B_D27

DDR_CKE1_DIMMA 9,18

9,18 DDR_CKE2_DIMMB
9,18 DDR_CS2_DIMMB#
9,18 DDR_B_BS2

DDR_B_BS2

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
M_ODT0
DDR_A_MA13

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_A_BS1 9,18
DDR_A_RAS# 9,18
DDR_CS0_DIMMA# 9,18
M_ODT0

9,18

9,18 DDR_B_BS0
9,18 DDR_B_WE#

DDR_B_CAS#

9,18 DDR_B_CAS#
9,18 DDR_CS1_DIMMB#

DDR_CS3_DIMMA# 9,18

9,18

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

M_ODT3

DDR_A_D32
DDR_A_D37

M_ODT3
DDR_B_D32
DDR_B_D36

M_CLK_DDR0
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D41
DDR_A_D40
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D42
DDR_A_D48
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

DDR_B_DQS#4
DDR_B_DQS4
C578
1.5P_50V
M_CLK_DDR#0

DDR_B_D38
DDR_B_D39

M_CLK_DDR1

DDR_B_D41
DDR_B_D40

C575
1.5P_50V
M_CLK_DDR#1

DDR_B_DM5
DDR_B_D42
DDR_B_D47

PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH

DDR_B_D53
DDR_B_D48

M_CLK_DDR1 9
M_CLK_DDR#1 9

DDR_A_DM6

DDR_B_DQS#6
DDR_B_DQS6

DDR_A_D55
DDR_A_D54

DDR_B_D50
DDR_B_D51

DDR_A_D60
DDR_A_D57

DDR_B_D56
DDR_B_D57

DDR_A_DQS#7
DDR_A_DQS7

DDR_B_DM7
DDR_B_D58
DDR_B_D59

DDR_A_D62
DDR_A_D63

MEM_SDATA
MEM_SCLK
R566
10K

+3.3V_RUN
R567
10K

CKE 0,1
B

C629
2.2U
10
0603
X7R

C630
0.1U_10V

SMbus address A0

VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
GNDPAD1
H1

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D2
DDR_B_D6

Place C275 2.2uF and C284 0.1uF <

500mils from DDR connector

DDR_B_D12
DDR_B_D9

M_CLK_DDR2 9
M_CLK_DDR#2 9
DDR_B_D10
DDR_B_D15

DDR_B_DM[0..7] 9
DDR_B_D[0..63] 9
DDR_B_DQS[0..7] 9
DDR_B_DQS#[0..7] 9
DDR_B_MA[0..15] 9,18

DDR_B_D20
DDR_B_D17

2.2U
0603
2.2U
0603
2.2U
10 0603
2.2U
10 0603
2.2U
10 0603
10
10

C281
X7R
C625
X7R
C627
X7R
C279
X7R
C278
X7R

DDR_B_DM1

NC_PM_EXTTS#1
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

2.2U
0603
2.2U
10 0603
2.2U
10 0603
2.2U
10 0603
2.2U
10 0603
10

C632
X7R
C631
X7R
C337
X7R
C634
X7R

C338
X7R
C339
X7R
C633
X7R
C340
X7R

1
1
1

2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10
2 0.1U
10 10

DDR_CKE3_DIMMB 9,18
DDR_B_MA15
DDR_B_MA14

Note:
Place C280,C277,C624,C626,C623 and
C632,C631,C337,C634 close to JDIM1
Place C281,C625,C627,C279,C278 and
C338,C339,C633,C340 close to JDIM2

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1 9,18
DDR_B_RAS# 9,18
DDR_CS0_DIMMB# 9,18
M_ODT2

DDR_B_MA13

9,18
+1.8V_SUS

DDR_CS3_DIMMB# 9,18
DDR_B_D33
DDR_B_D37
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_B_DM4
DDR_B_D34
DDR_B_D35

M_CLK_DDR2

DDR_B_D45
DDR_B_D44
DDR_B_DQS#5
DDR_B_DQS5

R271
1K
1%

C330
0.1U
10

R275
1K
1%

C331
0.1U
10

+0.9V_DDR_REF

C577
1.5P_50V
M_CLK_DDR#2
M_CLK_DDR3

DDR_B_D46
DDR_B_D43
DDR_B_D52
DDR_B_D49

C332
1000P
50

C574
1.5P_50V
M_CLK_DDR#3

Note: Place close to DIMM

M_CLK_DDR3 9
M_CLK_DDR#3 9

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

2
R315

+3.3V_RUN

1
10K

Title

QUANTA
COMPUTER
DDRII SODIMMX2

R316
10K

TYC_1775804-2

CLOCK 2,3 CKE 2,3

VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
GNDPAD2
H2

1
2

DDR_B_D18
DDR_B_D19

FOX_AS0A426-M2SN-7F

CLOCK 0,1
A

DDR_A_D22
DDR_A_D19

DDR_A_MA15
DDR_A_MA14

24 MEM_SDATA
24 MEM_SCLK
+3.3V_RUN
C282
2.2U
10
0603
X7R

DDR_B_DQS#2
DDR_B_DQS2

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

C280
X7R
C277
X7R
C624
X7R
C626
X7R
C623
X7R

0.1U_10V

9,18 DDR_A_CAS#
9,18 DDR_CS1_DIMMA#

NC_PM_EXTTS#0
DDR_A_DM2

DDR_B_D16
DDR_B_D21

C284

DDR_B_DM0

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

9,18 DDR_A_BS0
9,18 DDR_A_WE#

DDR_A_D20
DDR_A_D17

DDR_B_D4
DDR_B_D5

C275
2.2U
10
0603
X7R

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_DM[0..7] 9
DDR_A_D[0..63] 9
DDR_A_DQS[0..7] 9
DDR_A_DQS#[0..7] 9
DDR_A_MA[0..15] 9,18

DDR_B_D14
DDR_B_D11

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_D10
DDR_A_D15

VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54

9,18 DDR_CKE0_DIMMA
9,18 DDR_CS2_DIMMA#
9,18 DDR_A_BS2

DDR_B_DQS#1
DDR_B_DQS1

M_CLK_DDR0 9
M_CLK_DDR#0 9

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

DDR_A_D30
DDR_A_D27

DDR_B_D13
DDR_B_D8

DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

DDR_B_D3
DDR_B_D7

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

TOP

PC4800 DDR2 SDRAM

SO-DIMM (200P)

DDR_A_D12
DDR_A_D8

Place C635 2.2uF and C628 0.1uF <

500mils from DDR connector

DDR_A_DM3

DDR_B_DQS#0
DDR_B_DQS0

DDR_A_D29
DDR_A_D25

DDR_B_D0
DDR_B_D1

DDR_A_D23
DDR_A_D18

0.1U_10V

DDR_A_DQS#2
DDR_A_DQS2

JDIM1

DDR_A_D16
DDR_A_D21

C628

DDR_A_D3
DDR_A_D7

DDR_A_D14
DDR_A_D11

C635
2.2U
10
0603
X7R

DDR_A_DM0

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D5
DDR_A_D4

DDR_A_D9
DDR_A_D13

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_A_D6
DDR_A_D2

VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54

VREF
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50

DDR_A_DQS#0
DDR_A_DQS0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

PC4800 DDR2 SDRAM

SO-DIMM (200P)

DDR_A_D0
DDR_A_D1

BOT

+1.8V_SUS
JDIM2

SMbus address A4
D

Size

Document Number
MGD

Date:

Thursday, March 01, 2007

Rev
3A
Sheet
E

Note:
please close to DIMMA

1
1
1
1
1

2
2
2
2
2