1.

Inverter :
Schematic diagram :

Spice code :
* Main circuit: inv
M1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5.0
v2 vi gnd pulse(0 5 1n 1n 1n 10n 20n)
.tran 2n 100n
.print tran v(vo,gnd) v(vi,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
* End of main circuit: inv

Output waveform :

DC Analysis :
Spice code :
********* Simulation Settings - Parameters and SPICE Options *********
MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5.0
v2 vi 0 dc 5
.dc lin source v2 0 5 .1
.print dc v(vo)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"

********* Simulation Settings - Analysis section *********

********* Simulation Settings - Additional SPICE commands *********
.end

Output :

2.
a) NAND Gate :
Schematic diagram :

Spice code :
* Main circuit: NAND
M1 vo a N2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5.0
v2 a gnd pulse(0 5 1n 1n 1n 5n 10n)
v3 b gnd pulse(0 5 1n 1n 1n 20n 40n)
.tran 2n 100n
.print tran v(vo,gnd) v(b,gnd) v(a,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"

* End of main circuit: NAND

Output waveform :

b) NOR Gate :
Schematic diagram :

Spice Code :
* Main circuit: NOR
M1 vo a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 vo b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N7 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 vo b N7 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5.0
v2 a gnd pulse(0 5 1n 1n 1n 5n 10n)
v3 b gnd pulse(0 5 1n 1n 1n 20n 40n)
.tran 2n 100n
.print tran v(vo,gnd) v(b,gnd) v(a,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"

* End of main circuit: NOR

Output Waveform :

c) XOR Gate :
Schematic diagram :

Spice Code :
* Main circuit: XOR
M1 N24 N3 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 vo N4 N24 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 vo a N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N1 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N4 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N3 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N17 N4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 vo a N17 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 vo b N17 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 N17 N3 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 N4 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 N3 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

v1 vdd gnd 5.0

v2 a gnd pulse(0 5 1n 1n 1n 5n 10n)
v3 b gnd pulse(0 5 1n 1n 1n 20n 40n)
.tran 2n 100n
.print tran v(vo,gnd) v(b,gnd) v(a,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
*End of main circuit: XOR

Output Waveform :

d) Boolean expression :
Y=b(ac+ac)
For MOS transistor implementation :
Y= b+(a+c)(a+c)

Schematic diagram :

Spice Code :
* Main circuit: boolean
M1 Vo c1 N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Vo N7 N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 N1 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N1 N5 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M5 Vo b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

M6 N7 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N5 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 Vdd c1 N4 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 N4 N7 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 Vdd N5 N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 N3 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 Vdd b Vo Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M13 N7 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M14 N5 c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
v1 vdd gnd 5.0
v2 a gnd pulse(0 5 1n 1n 1n 10n 20)
v3 b gnd pulse(0 5 1n 1n 1n 15n 30n)
v4 c1 gnd pulse(0 5 1n 1n 1n 20n 40n)
.tran 2n 100n
.print tran v(Vo,gnd) v(c1,gnd) v(b,gnd) v(a,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
* End of main circuit: Boolean

Output Waveform :

3.
a) D Flip Flop :
Schematic Diagram :

Spice Code :
* Main circuit: D_FF
M1 Qb ck N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 N5 D Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 Q Qb Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 Qb ckb N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 N1 Q Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 ckb ck Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 Qb ckb N3 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N3 D Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 Q Qb Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M10 Qb ck N6 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M11 N6 Q Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M12 ckb ck Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u

v1 vdd gnd 5.0

v2 ck gnd PULSE(0 5 1n 1n 1n 5n 10n)
v3 D gnd PULSE(0 5 1n 1n 1n 20n 30n)
.tran 1n 50n
.print tran v(Qb,gnd) v(Q,gnd) v(D,gnd) v(ck,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
* End of main circuit: D_FF

Output Waveform :

b) JK Flip Flop :
Schematic Diagram :

Spice Code :
* Main circuit: JK_FF
M1 Q K N5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M2 Gnd Qb Q Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M3 Qb Q Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M4 N5 clk N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M5 Gnd Q N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M6 N1 J Qb Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M7 N2 clk N1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M8 N2 Qb Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
M9 N8 Qb Q Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u
M10 N8 K Vdd Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u
M11 N8 Q Vdd Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u
M12 Vdd clk N8 Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u

M13 Qb Q N7 Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u

M14 N7 clk Vdd Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u
M15 Vdd Qb N7 Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u
M16 Vdd J N7 Vdd PMOS L=2u W=44u AD=66p PD=24u AS=66p PS=24u

v1 vdd gnd 5.0

v2 J gnd PULSE(5 0 1n 1n 1n 30n 50n)
v3 K gnd PULSE(0 5 1n 1n 1n 40n 60n)
v4 clk gnd PULSE(0 5 1n 1n 1n 10n 20n)
.tran 2n 100n
.print tran v(Qb,gnd) v(Q,gnd) v(K,gnd) v(J,gnd) v(clk,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
* End of main circuit: JK_FF

Output Waveform :

4.
a1) Serial Adder :

May be used in signal-processing arithmetic where fast computation is important

but latency is unimportant.

Data format (LSB first):

Schematic Diagram :

Spice code :
********* Simulation Settings - General section *********
*************** Subcircuits *****************
.subckt full_adder a b ci co sum Gnd Vdd
MMOSFET_N_1 N_1 ci N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 N_2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_4 N_1 a N_3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_5 N_3 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u

MMOSFET_N_6 N_4 N_1 N_6 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_7 N_6 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_8 N_6 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_10 Gnd ci N_5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_9 N_6 ci Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_11 N_5 a N_7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_12 N_7 b N_4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_13 sum N_4 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_14 co N_1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_10 N_10 b N_4 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_11 N_12 a N_10 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_12 Vdd ci N_12 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_13 sum N_4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_14 N_4 N_1 N_11 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_1 ci N_9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_9 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_3 N_9 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_4 N_8 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_5 N_1 a N_8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_6 co N_1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_7 N_11 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_8 N_11 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_9 N_11 ci Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u

.ends
.subckt inv vi vo Gnd Vdd
MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.ends
.subckt NAND_3 a b c1 vo Gnd Vdd
MMOSFET_N_1 vo b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N_1 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 vo c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
.subckt AND2 a b vo Gnd Vdd
MMOSFET_N_1 N_1 a N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_1 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_1 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
Xinv_1 N_1 vo Gnd Vdd inv
.ends
.subckt D_FF_pos_edg D Q Qb R S clk Gnd Vdd
XNAND_3_1 N_1 Qb S Q Gnd Vdd NAND_3
XNAND_3_2 N_4 R Q Qb Gnd Vdd NAND_3
XNAND_3_3 N_5 N_1 S N_6 Gnd Vdd NAND_3
XNAND_3_4 R clk N_6 N_1 Gnd Vdd NAND_3
XNAND_3_5 clk N_5 N_1 N_4 Gnd Vdd NAND_3
XNAND_3_6 R D N_4 N_5 Gnd Vdd NAND_3
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XAND2_1 co N_5 N4 Gnd Vdd AND2
XD_FF_pos_edg_1 N1 co N_1 r1 set clk Gnd Vdd D_FF_pos_edg

XD_FF_pos_edg_2 N0 s2 N_2 r1 set clk Gnd Vdd D_FF_pos_edg

XD_FF_pos_edg_3 co c2 N_3 r1 set clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_4 s2 s1 N_4 r1 set clk Gnd Vdd D_FF_pos_edg
Xfull_adder_1 b a N4 N1 N0 Gnd Vdd full_adder
Xinv_1 ci N_5 Gnd Vdd inv
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5.0
v2 clk gnd PULSE(0 5 4n 1n 1n 5n 10n)
v4 R1 gnd PULSE(5 0 0 1n 1n 10n 100n)
v5 Set gnd 5
v6 ci gnd 0
v7 a gnd 5
v8 b gnd 5
.tran 2n 100n
.print tran v(co,gnd) v(s2,gnd) v(s1,gnd) v(c2,gnd) v(b,gnd) v(a,gnd) v(clk,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

a2) Parallel adder :

Schematic Diagram :

Spice Code :
.subckt full_adder a b ci co sum Gnd Vdd
MMOSFET_N_1 N_1 ci N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 N_2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_4 N_1 a N_3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_5 N_3 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_6 N_4 N_1 N_6 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_7 N_6 a Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_8 N_6 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_10 Gnd ci N_5 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u

MMOSFET_N_9 N_6 ci Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_11 N_5 a N_7 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_12 N_7 b N_4 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_13 sum N_4 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_14 co N_1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_10 N_10 b N_4 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_11 N_12 a N_10 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_12 Vdd ci N_12 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_13 sum N_4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_14 N_4 N_1 N_11 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_1 ci N_9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_9 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_3 N_9 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_4 N_8 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_5 N_1 a N_8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_6 co N_1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_7 N_11 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_8 N_11 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_9 N_11 ci Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
********* Simulation Settings - Parameters and SPICE Options *********
Xfull_adder_2 b2 a2 c2 co s2 Gnd Vdd full_adder
Xfull_adder_3 b1 a1 ci c2 s1 Gnd Vdd full_adder
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5
v2 a1 gnd PULSE(5 0 0 0 0 10n 20n)
v3 b1 gnd PULSE(5 0 0 0 0 20n 40n)

v4 a2 gnd PULSE(5 0 0 0 0 40n 80n)

v5 b2 gnd PULSE(5 0 0 0 0 20n 40n)
v6 ci gnd 0
.tran 2n 100n
.print tran v(co,gnd) v(s2,gnd) v(c2,gnd) v(b2,gnd) v(a2,gnd) v(s1,gnd) v(b1,gnd)
v(a1,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output waveform :

b) 4:1 Multiplexer :

Schematic Diagram :

Spice Code :
MMOSFET_N_5 y s1b N_12 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_6 N_12 s0 N_4 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_7 N_13 s0 i3 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_8 y s1 N_13 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_P_1 i3 s0b N_2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_2 s1b y Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_3 N_4 s0b N_5 Vdd PMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_P_4 N_5 s1 y Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u

MMOSFET_P_5 i1 s0 N_8 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p

PS=24u
MMOSFET_P_6 N_9 s1 y Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_1 N_10 s0b i0 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_P_7 N_8 s1b y Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 y s1b N_10 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_P_8 i0 s0 N_9 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 N_11 s0b i1 Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_4 y s1 N_11 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_10 s1b s1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_10 s1b s1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_N_9 s0b s0 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
MMOSFET_P_9 s0b s0 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u
AS=66p PS=24u
v1 vdd gnd 5.0
v2 i0 gnd 0
*PULSE(0 3 1n 1n 1n 10n 20n)
v3 i1 gnd 0
*PULSE(0 5 1n 1n 1n 20n 40n)
v4 i2 gnd 0
*PULSE(5 0 1n 1n 1n 20n 40n)
v5 i3 gnd 5
*PULSE(5 0 1n 1n 1n 4n 70n)
v6 s0 gnd PULSE(5 0 0n 0n 0n 20n 40n)
v7 s1 gnd PULSE(5 0 0n 0n 0n 40n 80n)
.tran 2n 200n
.print tran v(y,gnd) v(s1,gnd) v(s0,gnd)
*v(i3,gnd) v(i2,gnd) v(i1,gnd) v(i0,gnd) v(s1,gnd) v(s0,gnd)
.include "C:\Program Files\Tanner EDA\Demo\T-Spice\models\ml2_20.md"
********* Simulation Settings - Analysis section *********

********* Simulation Settings - Additional SPICE commands *********

.end

Output Waveform :

c) Barrel Shifter :
Barrel shifter operation

Accepts 2n data inputs and n control signals, producing n data outputs

Selects arbitrary contiguous n bits out of 2n input bits .

Examples:
o
o
o

right shift: data into top, 0 into bottom;

left shift: 0 into top, data into bottom;
rotate: data into top and bottom.

Schematic Diagram :

Spice Code :
********* Simulation Settings - General section *********
********* Simulation Settings - Parameters and SPICE Options *********
MMOSFET_N_14 In1 shift3 Out0 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u

MMOSFET_N_5 In0 shift2 Out2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_6 In1 shift1 Out2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_15 In2 shift2 Out0 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_7 In2 shift0 Out2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_16 In3 shift1 Out0 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_8 In3 shift3 Out2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_9 In0 shift1 Out1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_10 In1 shift0 Out1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_1 In0 shift3 Out3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_11 In2 shift3 Out1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 In1 shift2 Out3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_12 In3 shift2 Out1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 In2 shift1 Out3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_13 In0 shift0 Out0 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_4 In3 shift0 Out3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
vSource_v_dc_1 Vdd Gnd 5.0
********* Simulation Settings - Analysis section *********
*v1 vdd gnd 5.0
*v2 In0 gnd PULSE(0 5 4n 1n 1n 5n 10n)v3 In0 gnd 5
v2 In0 gnd PULSE(0 5 4n 1n 1n 5n 10n)
v3 In1 gnd PULSE(0 5 4n 1n 1n 10n 20n)
v4 In2 gnd PULSE(0 5 4n 1n 1n 20n 40n)
v5 In3 gnd PULSE(0 5 4n 1n 1n 40n 80n)
v6 shift0 gnd 0
v7 shift1 gnd 0
v8 shift2 gnd 5
v9 shift3 gnd 0
.tran 2n 100n

.print tran v(Out0,gnd) v(Out1,gnd) v(Out2,gnd) v(Out3,gnd)

*v(shift0,gnd) v(shift1,gnd) v(shift2,gnd) v(shift3,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

5. Differential amplifier:

Schematic Diagram :

Spice Code :
MMOSFET_N_1 N_1 vgs1 N_2 Gnd NMOS L=1u W=2u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 vo vgs2 N_2 Gnd NMOS L=1u W=2u AD=66p PD=24u AS=66p
PS=24u
vSource_v_dc_1 N_4 Gnd 5.0
MMOSFET_P_1 Vdd N_1 N_1 Vdd PMOS L=1u W=2u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 N_2 N_4 Gnd Gnd NMOS L=1u W=2u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 Vdd N_1 vo Vdd PMOS L=1u W=2u AD=66p PD=24u AS=66p
PS=24u

v1 vgs1 gnd 5

v2 vgs2 gnd 3
v3 vdd gnd 5.0
.dc lin source v1 0 5 .1
.print dc v(vo)
.include "G:\model_1u.md"
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Additional SPICE commands *********
.end

Output :

Symbol :

6. Schmitt trigger :

Scematic Diagram :

Spice code :
MMOSFET_N_1 vo vi N_1 Gnd NMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_2 N_1 vi Gnd Gnd NMOS L=2u W=2u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_2 vi Vdd Vdd PMOS L=2u W=2u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_3 Vdd vo N_1 Gnd NMOS L=2u W=6u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo vi N_2 Vdd PMOS L=2u W=5u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 Gnd vo N_2 Vdd PMOS L=2u W=6u AD=66p PD=24u AS=66p
PS=24u
vSource_v_sine_1 vi Gnd sin 0 5 1000 0.0 0.0 0.0
v2 vdd gnd 5.0
*v1 vi 0 5

*.dc lin source v1 0 5 .1

********* Simulation Settings - Analysis section *********
.tran 2u 4m
.print tran v(vi,gnd) v(vo,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

7. Counters
Asynchronous up counter :
A counter is a very simple device. It usually counts from 0 to N. Some counters allow
you to hold the value or to increment one at a time. We're going to build a very simple
counter using D flip flops. This counter is called asynchronous because not all flip flops
are hooked to the same clock.
Each of the D flip flop used here is positive edge triggered and acts in always
toggle mode by its inverting output and connecting back to the input. The external clock
is applied to the first flip flop. So Q0 toggles with the positive edge of the clock. Q0 is
fed to the clkock input of the next D flipflop, so Q1 toggles with the positive edge of Q0 .
So Q3Q2Q1Q0 generates the desired sequence 0000, 0001, 0010, .... 1111 .

Spice Code :
.subckt inv vi vo Gnd Vdd
MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.ends

.subckt NAND_3 a b c1 vo Gnd Vdd

MMOSFET_N_1 vo b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N_1 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 vo c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
.subckt D_FF_pos_edg D Q Qb R S clk Gnd Vdd
XNAND_3_1 N_1 Qb S Q Gnd Vdd NAND_3
XNAND_3_2 N_4 R Q Qb Gnd Vdd NAND_3
XNAND_3_3 N_5 N_1 S N_6 Gnd Vdd NAND_3
XNAND_3_4 R clk N_6 N_1 Gnd Vdd NAND_3
XNAND_3_5 clk N_5 N_1 N_4 Gnd Vdd NAND_3
XNAND_3_6 R D N_4 N_5 Gnd Vdd NAND_3
.ends
********* Simulation Settings - Parameters and SPICE Options *********
Xinv_2 N_7 N_4 Gnd Vdd inv
Xinv_3 N_6 N_3 Gnd Vdd inv
Xinv_4 N_1 N_2 Gnd Vdd inv
XD_FF_pos_edg_1 N_5 N_8 Q0 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_2 N_4 N_7 Q1 R1 S N_8 Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_3 N_3 N_6 Q2 R1 S N_7 Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_4 N_2 N_1 Q3 R1 S N_6 Gnd Vdd D_FF_pos_edg
Xinv_1 N_8 N_5 Gnd Vdd inv
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5.0
v2 clk gnd PULSE(0 5 4n 1n 1n 5n 10n)
*v3 D1 gnd PULSE(0 5 0 1n 1n 15n 30n)
v4 R1 gnd PULSE(5 0 0 1n 1n 5n 100n)
v5 S gnd 5
.tran 2n 100n
.print tran v(Q3,gnd) v(Q2,gnd) v(Q1,gnd) v(Q0,gnd) v(clk,gnd)

.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools

v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

Asynchronous down counter :

Spice Code :
********* Simulation Settings - General section *********
*************** Subcircuits *****************

.subckt inv vi vo Gnd Vdd

MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.ends
.subckt NAND_3 a b c1 vo Gnd Vdd
MMOSFET_N_1 vo b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N_1 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 vo c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
.subckt D_FF_pos_edg D Q Qb R S clk Gnd Vdd
XNAND_3_1 N_1 Qb S Q Gnd Vdd NAND_3
XNAND_3_2 N_4 R Q Qb Gnd Vdd NAND_3
XNAND_3_3 N_5 N_1 S N_6 Gnd Vdd NAND_3
XNAND_3_4 R clk N_6 N_1 Gnd Vdd NAND_3
XNAND_3_5 clk N_5 N_1 N_4 Gnd Vdd NAND_3
XNAND_3_6 R D N_4 N_5 Gnd Vdd NAND_3
.ends
********* Simulation Settings - Parameters and SPICE Options *********
Xinv_2 N_4 N_3 Gnd Vdd inv
Xinv_3 N_6 N_5 Gnd Vdd inv
Xinv_4 N_8 N_7 Gnd Vdd inv
XD_FF_pos_edg_1 N_1 N_2 Q0 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_2 N_3 N_4 Q1 R1 S Q0 Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_3 N_5 N_6 Q2 R1 S Q1 Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_4 N_7 N_8 Q3 R1 S Q2 Gnd Vdd D_FF_pos_edg
Xinv_1 N_2 N_1 Gnd Vdd inv
********* Simulation Settings - Analysis section *********
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5.0
v2 clk gnd PULSE(0 5 4n 1n 1n 10n 20n)
*v3 D1 gnd PULSE(0 5 0 1n 1n 15n 30n)
v4 R1 gnd PULSE(5 0 0 1n 1n 5n 100n)

v5 S gnd 5
.tran 2n 100n
.print tran v(Q3,gnd) v(Q2,gnd) v(Q1,gnd) v(Q0,gnd) v(clk,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

Synchronous up counter :

The clock frequency can be increased by using synchronous counter whose 4-bit
implementation using positive edge triggered D-FF is shown below. The LSB Q0 is
always toggling with the positive edge of the clock. The next bit Q1 toggles with the
active clock edge when Q0 is just before the active clock edge. Similarly Q2 toggles
with the active clock edge when both Q0 and Q1 are 1 just before the active clock edge.
Similar is the case for Q3.
So the first flipflop always acts in the toggle mode and the second D-FF acts in
controlled toggle mode. This is done by feeding the output of the flipflop to one input of
the XOR gate whose output is given to the input of that flipflop. The other input of the
XOR gate is the toggle input.

Schematic Diagram :

Spice Code :

********* Simulation Settings - General section *********

*************** Subcircuits *****************
.subckt inv vi vo Gnd Vdd
MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.ends
.subckt NAND_3 a b c1 vo Gnd Vdd
MMOSFET_N_1 vo b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N_1 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 vo c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
.subckt AND2 a b vo Gnd Vdd
MMOSFET_N_1 N_1 a N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_1 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_1 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
Xinv_1 N_1 vo Gnd Vdd inv
.ends
.subckt D_FF_pos_edg D Q Qb R S clk Gnd Vdd
XNAND_3_1 N_1 Qb S Q Gnd Vdd NAND_3
XNAND_3_2 N_4 R Q Qb Gnd Vdd NAND_3
XNAND_3_3 N_5 N_1 S N_6 Gnd Vdd NAND_3
XNAND_3_4 R clk N_6 N_1 Gnd Vdd NAND_3
XNAND_3_5 clk N_5 N_1 N_4 Gnd Vdd NAND_3
XNAND_3_6 R D N_4 N_5 Gnd Vdd NAND_3
.ends
.subckt XOR2 a b vo Gnd Vdd
Xinv_2 b N_2 Gnd Vdd inv

MMOSFET_N_1 vo a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p

PS=24u
MMOSFET_N_2 N_1 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo a N_5 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 vo N_2 N_3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo b N_5 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_4 N_3 N_4 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_3 N_5 N_4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_4 N_5 N_2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
Xinv_1 a N_4 Gnd Vdd inv
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XD_FF_pos_edg_1 N_2 Q0 N_9 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_2 N_4 Q1 N_6 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_3 N_7 Q2 N_3 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_4 N_8 Q3 N_1 R1 S clk Gnd Vdd D_FF_pos_edg
XXOR2_3 Q3 N_10 N_8 Gnd Vdd XOR2
XAND2_1 Q0 Q1 N_5 Gnd Vdd AND2
XAND2_2 N_5 Q2 N_10 Gnd Vdd AND2
XXOR2_1 Q1 Q0 N_4 Gnd Vdd XOR2
XXOR2_2 Q2 N_5 N_7 Gnd Vdd XOR2
Xinv_1 Q0 N_2 Gnd Vdd inv
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5.0
v2 clk gnd PULSE(0 5 4n 1n 1n 5n 10n)
v4 R1 gnd PULSE(5 0 0 1n 1n 5n 100n)
v5 S gnd 5
.tran 2n 100n
.print tran v(Q3,gnd) v(Q2,gnd) v(Q1,gnd) v(Q0,gnd) v(clk,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Waveform :

Synchronous down counter :

Spice Code :
.subckt inv vi vo Gnd Vdd
MMOSFET_N_1 vo vi Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo vi Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
.ends
.subckt NAND_3 a b c1 vo Gnd Vdd
MMOSFET_N_1 vo b N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 N_1 c1 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_P_3 vo c1 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
.ends
.subckt AND2 a b vo Gnd Vdd
MMOSFET_N_1 N_1 a N_2 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_N_2 N_2 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 N_1 a Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 N_1 b Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
Xinv_1 N_1 vo Gnd Vdd inv
.ends
.subckt D_FF_pos_edg D Q Qb R S clk Gnd Vdd
XNAND_3_1 N_1 Qb S Q Gnd Vdd NAND_3
XNAND_3_2 N_4 R Q Qb Gnd Vdd NAND_3
XNAND_3_3 N_5 N_1 S N_6 Gnd Vdd NAND_3
XNAND_3_4 R clk N_6 N_1 Gnd Vdd NAND_3
XNAND_3_5 clk N_5 N_1 N_4 Gnd Vdd NAND_3
XNAND_3_6 R D N_4 N_5 Gnd Vdd NAND_3
.ends
.subckt XOR2 a b vo Gnd Vdd
Xinv_2 b N_2 Gnd Vdd inv

MMOSFET_N_1 vo a N_1 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p

PS=24u
MMOSFET_N_2 N_1 b Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_1 vo a N_5 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_3 vo N_2 N_3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_2 vo b N_5 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u
MMOSFET_N_4 N_3 N_4 Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_3 N_5 N_4 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
MMOSFET_P_4 N_5 N_2 Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p
PS=24u
Xinv_1 a N_4 Gnd Vdd inv
.ends
********* Simulation Settings - Parameters and SPICE Options *********
XD_FF_pos_edg_1 N_2 N_1 Q0 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_2 N_4 N_3 Q1 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_3 N_7 N_6 Q2 R1 S clk Gnd Vdd D_FF_pos_edg
XD_FF_pos_edg_4 N_8 N_9 Q3 R1 S clk Gnd Vdd D_FF_pos_edg
XXOR2_3 N_9 N_10 N_8 Gnd Vdd XOR2
XAND2_1 N_1 N_3 N_5 Gnd Vdd AND2
XAND2_2 N_5 N_6 N_10 Gnd Vdd AND2
XXOR2_1 N_3 N_1 N_4 Gnd Vdd XOR2
XXOR2_2 N_6 N_5 N_7 Gnd Vdd XOR2
Xinv_1 N_1 N_2 Gnd Vdd inv
********* Simulation Settings - Analysis section *********
v1 vdd gnd 5.0
v2 clk gnd PULSE(0 5 4n 1n 1n 5n 10n)
v4 R1 gnd PULSE(5 0 0 1n 1n 5n 100n)
v5 S gnd 5
.tran 2n 100n
.print tran v(Q3,gnd) v(Q2,gnd) v(Q1,gnd) v(Q0,gnd) v(clk,gnd)
.include "C:\Documents and Settings\bsk\My Documents\Tanner EDA\Tanner Tools
v12.1\T-Spice\models\ml2_20.md"
********* Simulation Settings - Additional SPICE commands *********
.end

Output Wave form :