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A CLA c1 Symd

This document contains a Verilog module for a combinational logic circuit with 3 inputs and 1 output. The module contains an AND gate and an OR gate connected with a wire. The document also includes simulation parameters that toggle the input signals over time.

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Ali Duraz
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15 views1 page

A CLA c1 Symd

This document contains a Verilog module for a combinational logic circuit with 3 inputs and 1 output. The module contains an AND gate and an OR gate connected with a wire. The document also includes simulation parameters that toggle the input signals over time.

Uploaded by

Ali Duraz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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// DSCH 2.

6c
// 1/8/2003 4:06:18 AM
// C:\Documents and Settings\Bear\Desktop\dsch2\A_CLA_c1_sym.sch
module A_CLA_c1_sym( g0,p0,c0,c1);
input g0,p0,c0;
output c1;
wire w5;
and #(15) and2_A_1(w5,c0,g0);
or #(15) or2_A_2(c1,p0,w5);
endmodule
// Simulation parameters in Verilog Format
always
#1000 g0=~g0;
#2000 p0=~p0;
#3000 c0=~c0;
//
//
//
//

Simulation parameters
g0 CLK 10 10
p0 CLK 20 20
c0 CLK 30 30

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