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SystemVerilog
Functional Coverage
Ahmed Hemani
System Architecture and Methodology Group
Department of Electronic and Computer Systems
School of ICT, KTH
Functional Coverage
Functional Coverage is used as a quantified metric to
Gauge how far we are from completion
Reduce redundancy
Redirect simulation resources to where it is needed
Functional Coverage is
User specified and not automatic like code coverage
Based on design specification/intent and not on
implementation
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Functional Coverage Constructs
The SystemVerilog functional coverage constructs
enable:
Coverage of variables and expressions, as well as cross
coverage between them.
Automatic as well as user-defined coverage bins.
Associate bins with sets of values, transitions, or cross
products.
Filtering conditions at multiple levels.
Events and sequences to automatically trigger coverage
sampling.
Procedural activation and query of coverage.
Optional directives to control and regulate coverage.
Covergroup
covergroup is like a user defined type that encapsulates
and specifies the coverage
It can be defined in a package, module, program,
interface or class
Once defined multiple instances can be created using new
Parameters to new() enable customization of different
instances
Ref argument enables different variables to be sampled by different
instances of covergroup
covergroup cg; . . . Endgroup
cg cg_inst = new;
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Triggered by
Clocking event/procedural sample () or strobe
Block event
Coverage point triggered by execution of a named block, task, function
or class method.
Coverage points
Variable or expression
Bins explicitly defined or automatically inferred
enum { red, green, blue } color;
covergroup g1 @(posedge clk);
c: coverpoint color;
endgroup
Covergroup
enum { red, green, blue } color;
bit [3:0] pixel_adr, pixel_offset, pixel_hue;
covergroup g2 @(posedge clk);
Hue: coverpoint pixel_hue;
Offset: coverpoint pixel_offset;
AxC: cross color, pixel_adr;//cross 2 variables (implicitly
//declared coverpoints)
all: cross color, Hue, Offset;//cross 1 variable and 2 coverpoints
endgroup
Cross coverage between different coverpoints
A coverage group can also specify one or more options to
control and regulate how coverage data is structured and
collected.
Coverage options can be specified for the coverage group
as a whole, or for specific items within the coverage group,
that is, any of its coverage points or crosses.
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Covergroup in classes
Declaring covergroups in class elegantly combines the
constrained random stimuli generation with its coverage in
one construct.
An implicit variable corresponding to covergroup name is
declared.
The covergroup must be explicitly instantiated using new
Covergroups can define coverage model for local and
protected members
A class can have more than one covergroups
class MC;
logic [3:0] m_x;
local logic m_z;
bit m_e;
covergroup cv1 @(posedge clk); coverpoint m_x; endgroup
covergroup cv2 @m_e; coverpoint m_z; endgroup
endclass
class xyz;
bit [3:0] m_x;
int m_y;
bit m_z;
covergroup cov1 @m_z; // embedded covergroup
coverpoint m_x;
coverpoint m_y;
endgroup
function new(); cov1 = new; endfunction
endclass
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Coverage points
A covergroup can contain one or more coverage points that
are integral variables or integral expressions.
Coverage points imply a set of bins associated with its
sampled values or its value transitions.
The bins can be explicitly defined by the user or automatically
created by SystemVerilog.
A coverage point creates a hierarchical scope, and can be
labeled. Label is the name of the coverage point.
If the label is omitted and the coverage point is associated with
a single variable then the variable name becomes the name of
the coverage point.
This name can be used to add this coverage point to a cross
coverage specification, or to access the methods of the
coverage point.
bit [9:0] v_a; // the maximum value is 1023
covergroup cg @(posedge clk);
coverpoint v_a{
bins a = {[0:63],65}; // single a bin collects v_a
// 65 b bins
bins b[] = {[127:150],[148:191]}; //overlapping values
bins c[] = {200,201,202}; // 3 c bins
bins d = {[1000:$]}; // single d bin; $ is 1023
bins others[] = default;} // everything else
endgroup
To conditionally disable sampling use the iff construct
covergroup g4;
coverpoint s0 iff (!reset);
endgroup
bins fixed1 [] = {1:10;1,4,7}; // 13 bins are created
bins fixed2 [4] = {1:10;1,4,7}; // 4 bins are created
// with distribution <1,2,3>, <4,5,6>, <7,8,9>, <10,1,4,7>
The bins construct allows creation of bins
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Generic Coverage Groups
covergroup gc (ref int ra, int low, int high ) @(posedge clk);
coverpoint ra //sample variable passed by reference
{
bins good = { [low : high] };
bins bad[] = default;
}
endgroup
...
int va, vb;
gc c1 = new( va, 0, 50 ); // cover variable va in the
//range 0 to 50
gc c2 = new( vb, 120, 600 ); // cover variable vb in
//the range 120 to 600
Generic coverage groups can be written by passing their
traits as arguments to the constructor.
Bins for transitions
In many cases, we are not only interested in knowing if certain
values or value ranges happen.
We are also interested in knowing if transition between, two
values or two value ranges happen.
Transition is coverage is often more interesting in control
scenarios, whereas value coverage is more interesting in
datapath scenarios.
One simple but potent application is to log if at the SOC/chip
level all top level wires make transition from 01 and 1 0
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Specifying transitions
A trans_list specifies one or more sets of ordered value transitions of the
coverage point. value1 and value2 are successive and consecutive
sample points
bins <name> = {value1 => value2}
// a sequence of transitions
bins <name> = {val1=> val3 => val4 => val5};
// a set of transitions
bins <name> = {1,5 => 6,7}; // 1=>6, 1=>7, 5=>6, 5=>7
// Consecutive repetitions of transitions
bins <name> = { 3 [* 5]}; // 3=>3=>3=>3=>3
// An example of a range of repetition is:
bins <name> = { 3 [* 3:5]}; // 3=>3=>3, 3=>3=>3=>3,
3=>3=>3=>3=>3
To specify occurrence of repetition that is not consecutive
bins <name> = {3 [ 3]}; // 3 => ... =>3 ... =>3
// ... Represents transitions that does not contain value 3
covergroup cg @(posedge clk);
coverpoint v_a {
// sa is incremented whenever any of the following xition happens
// 4=>5=>6, 7=>16, 8=>16, 9=>16, 15=>16, 7=>27, 8=>27, 9=>27, 15=>27
bins sa = (4 => 5 => 6), ([7:9],15=>16,27);
// same set of xitions as above but now one bin for each xition
bins sb[] = (4 => 5 => 6), ([7:9],15=>16,27);
bins allother = default sequence;}
endgroup
The trans_list can specify one or more sets of ordered
value transitions
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Automatic bin creation
SystemVerilog creates implicit bins, when the coverage point does not
explicitly specifies it using the bins construct
The size of the automatic bin creation is decided by
the cardinality of coverage point as long.
The size cannot exceed the auto_bin_max option.
If the auto_bin_max is less than the cardinality of the coverage point,
the values are equitably distributed among the bins.
e.g. if the cardinality of coverage point is 2
3
,i.e, 8 and the
auto_bin_max is 3, the values are distributed as
<0:1><2:3><4,5,6,7>
Bins created automatically only consider 2 state values
Wildcard for bins
// The count of transition bin T0_3 is incremented for
// the transitions: 00 => 10 00 => 11 01 => 10 01 => 11
// (as if by (0,1=>2,3)):
wildcard bins T0_3 = (2b0x => 2b1x);
Normally, when a bin value has X or Z, the comparison is literal.
Literal comparison is performed using === operator
The bins construct can be qualified with wildcard keyword
Then the wildcard character ? can be used
The =?= operator is used in such a case
// The count of bin g12_16 is incremented when the
// sampled variable is between 12 and 16
wildcard bins g12_16 = { 4b11?? };
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ignore_bins & illegal_bins
covergroup cg23;
coverpoint a
{ ignore_bins ignore_vals = {7,8};
ignore_bins ignore_trans = (1=>3=>5);}
endgroup
covergroup cg3;
coverpoint b
{ illegal_bins bad_vals = {1,2,3};
illegal_bins bad_trans = (4=>5=>6);}
endgroup
Just like False paths, certain parts of stimuli space might not be
interesting or might even be illegal
In principle, constraints should ensure that only relevant values
are generated.
Values and Transitions can be ignored and declared illegal using
ignore_bins and illegal_bins construct. When a value
for illegal_bins matches a runtime error is generated
Cross Coverage
Coverage points measures occurrences of individual values,
Cross coverage measures occurrences of combination of
values
Did I generate all interesting combinations of values?
Did I inject corrupted packets into all ports?
Did the FSM visit all states when the buffer was full?
A coverage group can specify cross coverage between two
or more coverage points or variables.
Cross coverage is specified using the cross construct.
When a variable V is part of a cross coverage,
SystemVerilog implicitly creates a coverage point for the
variable, as if it had been created by the statement
coverpoint V.
Thus, a cross involves only coverage points.
Expressions cannot be used directly in a cross; a coverage
point must be explicitly defined first.
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Declaring cross coverage
The label for a cross declaration provides an optional
name. The label also creates a hierarchical scope for the
bins defined within the cross.
The cross construct specifies the cartesian product of N
coverpoints.
bit [3:0] a, b;
covergroup cov @(posedge
clk);
aXb : cross a, b;
endgroup
Cross coverage is allowed only between coverage points
defined within the same coverage group
SystemVerilog creates
implicity coverpoints
and 16 bins each for
variables a and b
The label aXb implies a coverpoint with 256 bins
bit [31:0] a_var;
bit [3:0] b_var;
covergroup cov3 @(posedge clk);
A: coverpoint a_var {bins yy[] = {[0:9] };}
CC: cross b_var, A;
endgroup
The cross of two coverage points creates 16 * 10 = 160 cross product bins:
<auto[0], yy[0]>
<auto[0], yy[1]>
...
<auto[0], yy[9]>
<auto[1], yy[0]>
...
<auto[15], yy[9]>
// an expression must be declared as an explicit
// coverpoint before using in the cross construct
bit [3:0] a, b, c;
covergroup cov2 @(posedge clk);
BC: coverpoint b+c;
aXb : cross a, BC;
endgroup
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binsof and intersect
To manipulate the coverage data and filter it binsof and
intersect constructs are useful
The binsof construct yields the bins of its expression
The resulting bins can be further selected by including (or excluding)
only the bins whose associated values intersect a desired set of values.
binsof( x ) intersect { y }
denotes the bins of coverage point x whose values intersect the range given
by y. Its negated form:
! binsof( x ) intersect { y }
denotes the bins of coverage point x whose values do not intersect the range
given by y.
The open_value_range syntax can specify a single value, a range of
values, or an open range, which denotes the following:
[$ : value] => The set of values less than or equal to value
[value : $] => The set of values greater or equal to value
The bins selected can be combined with other selected bins using the
logical operators && and ||
bit [7:0] v_a, v_b;
covergroup cg @(posedge clk);
a: coverpoint v_a
{bins a1 = { [0:63] };
bins a2 = { [64:127] };
bins a3 = { [128:191] };
bins a4 = { [192:255] };
}
b: coverpoint v_b
{bins b1 = {0};
bins b2 = { [1:84] };
bins b3 = { [85:169] };
bins b4 = { [170:255] };
}
c : cross v_a, v_b
{bins c1 = ! binsof(a) intersect {[100:200]};
bins c2 = binsof(a.a2) || binsof(b.b2);
bins c3 = binsof(a.a1) && binsof(b.b4);
}
endgroup
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Specifying Illegal Cross Products
A group of bins can be marked as illegal by specifying a select expression
using illegal_bins. For example:
covergroup zz(int bad);
cross x, y
{
illegal_bins foo = binsof(y) intersect {bad};
}
endgroup
All cross products that satisfy the select expression are excluded from
coverage, and a run-time error is issued.