VHDL CODE FOR MAC UNIT
entity macunit is
Port ( x,y : in STD_LOGIC_VECTOR (2 downto 0);
clk1,rst1 : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (5 downto 0));
end macunit;
architecture Behavioral of macunit is
component pipo
Port ( u : in STD_LOGIC_VECTOR (5 downto 0);
clock : in STD_LOGIC;
rst : in STD_LOGIC;
w : out STD_LOGIC_VECTOR (5 downto 0));
end component;
component multiplier
Port ( l,m : in STD_LOGIC_VECTOR (2 downto 0);
n : out STD_LOGIC_VECTOR (5 downto 0));
end component;
signal t:std_logic_vector(5 downto 0);
begin
g0: multiplier port map(x,y,t);
g1: pipo port map(t,clk1,rst1,z);
end Behavioral;
entity multiplier is
Port ( l,m : in STD_LOGIC_VECTOR (2 downto 0);
n : out STD_LOGIC_VECTOR (5 downto 0));
end multiplier;
architecture Behavioral of multiplier is
component and1
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
component hadder
port( i,j : in STD_LOGIC;
su,ca : out STD_LOGIC);
end component;
component fulladd
Port ( d,e,f : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end component;
component or1
Port ( a1,b1 : in STD_LOGIC;
c1 : out STD_LOGIC);
end component;
signal p,q: std_logic;
signal r : std_logic_vector( 8 downto 0);
signal s : std_logic_vector ( 3 downto 0);
signal si: std_logic_vector(3 downto 1);
signal sic: std_logic_vector(3 downto 1);
signal sumor: std_logic;
begin
l0: and1 port map ( l(0),m(0),r(0));
l1: and1 port map ( l(1),m(0),r(1));
l2: and1 port map ( l(0),m(1),r(2));
l3: and1 port map ( l(2),m(0),r(3));
l4: and1 port map ( l(1),m(1),r(4));
l5: and1 port map ( l(0),m(2),r(5));
l6: and1 port map ( l(2),m(1),r(6));
l7: and1 port map ( l(1),m(2),r(7));
l8: and1 port map ( l(2),m(2),r(8));
n(0)<= r(0);
m1: hadder port map (r(1),r(2),n(1),s(1));
m2: hadder port map (s(1),r(3),si(1),sic(1));
m3: hadder port map (r(4),r(5),si(2),sic(2));
m4: hadder port map (si(1),si(2),n(2),s(2));
m5: hadder port map (sic(1),sic(2),si(3),sic(3));
m8: or1 port map (s(2),si(3),sumor);
m6: fulladd port map (sumor,r(6),r(7),n(3),s(3));
m7: fulladd port map (s(3),sic(3),r(8),n(4),n(5));
end Behavioral;
entity and1 is
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end and1;
architecture Behavioral of and1 is
begin
c<= a and b;
end Behavioral;
entity or1 is
Port ( a1,b1 : in STD_LOGIC;
c1 : out STD_LOGIC);
end or1;
architecture Behavioral of or1 is
begin
c1<= a1 or b1;
end Behavioral;
entity hadder is
Port ( i,j : in STD_LOGIC;
su,ca : out STD_LOGIC);
end hadder;
architecture Behavioral of hadder is
begin
su<= i xor j;
ca<= i and j;
end Behavioral;
entity fulladd is
Port ( d,e,f : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladd;
architecture Behavioral of fulladd is
component and1
Port ( a,b : in STD_LOGIC;
c : out STD_LOGIC);
end component;
begin
sum <= d xor e xor f;
carry <= ((d and e) or ( e and f ) or ( f and d));
end Behavioral;
entity pipo is
Port ( u : in STD_LOGIC_VECTOR (5 downto 0);
clock : in STD_LOGIC;
rst : in STD_LOGIC;
w : out STD_LOGIC_VECTOR (5 downto 0));
end pipo;
architecture Behavioral of pipo is
component dff
port(data,clk,reset : in STD_LOGIC;
output : out STD_LOGIC);
end component;
begin
d0: dff port map ( u(0),clock,rst,w(0));
d1: dff port map ( u(1),clock,rst,w(1));
d2: dff port map ( u(2),clock,rst,w(2));
d3: dff port map ( u(3),clock,rst,w(3));
d4: dff port map ( u(4),clock,rst,w(4));
d5: dff port map ( u(5),clock,rst,w(5));
end Behavioral;
entity dff is
Port ( data,clk,reset : in STD_LOGIC;
output : out STD_LOGIC);
end dff;
architecture Behavioral of dff is
begin
process(clk)
begin
if(reset='1') then output<= '0';
elsif( clk'event and clk='1') then output<= data;
end if;
end process;
end Behavioral;
(a)
(b)
FIG 6.3 SCHEMATIC DIAGRAM FOR MAC UNIT
FIG 6.4 WAVEFORM FOR MAC UNIT
