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Low-Voltage Pulsewidth Control Loops For SOC Applications

The document proposes a new low-voltage pulsewidth control loop (PWCL) architecture that features fixed rising edges to work cooperatively with phase-locked loops (PLLs) and delay-locked loops (DLLs). It introduces a new duty-cycle detector and pulse generator to replace components in conventional PWCLs. Simulation and test results show the new PWCL can operate at higher frequencies with lower voltages than previous designs, making it suitable for system-on-chip applications.

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陳鍾誠
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331 views

Low-Voltage Pulsewidth Control Loops For SOC Applications

The document proposes a new low-voltage pulsewidth control loop (PWCL) architecture that features fixed rising edges to work cooperatively with phase-locked loops (PLLs) and delay-locked loops (DLLs). It introduces a new duty-cycle detector and pulse generator to replace components in conventional PWCLs. Simulation and test results show the new PWCL can operate at higher frequencies with lower voltages than previous designs, making it suitable for system-on-chip applications.

Uploaded by

陳鍾誠
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Low-Voltage Pulsewidth Control

Loops for SOC Applications

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002

Po-Hui Yang, Jinn-Shyan Wang

Speaker: Wen-Lung Chang


Date: 10. 28.2009
Outline
 Abstract & Introduction
 Circuit architecture
 Experimental results
 Conclusion
Abstract & Introduction

 In this paper, adopts the conventional PWCL,


but with a new duty-cycle detector and a pulse
generator.

 Using this architecture, the output of PWCL


has fixed rising edge.

 This architecture can combine PLL/DLL with


PWCL to perform phase locking and adjust
pulsewidth.
Abstract & Introduction

 The design goal in this paper is proposing a


PWCL operates at low-voltage and high-
frequency.

 The features of operating at low voltage,


providing variable duty cycle, and being able
to cooperate with PLL/DLL make the new
PWCL suitable for system-on-chip
applications.
Circuit architecture

Conventional PWCL
Circuit architecture

phase-fixed PWCL.
Conventional PWCL
 There are two problems when using this circuit.

 When the PWCL works together with PLL/DLLs,


the phase change by the PWCL disturbs.

 The charge pumps and differential amplifier are


used to act as a duty-cycle detector to generate
the control voltage for the pulse generator.
Conventional PWCL
New building blocks
Simulations waveforms
New building blocks
Simulations waveforms
Experimental results
 The pulsewidth of the clock to the
multiplier is 0.62 ns, and the jitter is 92 ps.
Experimental results
Conclusion
 In the new building blocks, the maximum clock
frequency can be increased tremendously.
 Allthe building blocks used in the new PWCL
have simple circuit structures, which makes the
PWCL suitable for low-voltage operation.

 The measurement results of the test chip


designed with a 0.35-um CMOS with only 1.8-V
prove the feasibility of the proposed techniques

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