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ECE 301 - Digital Electronics: Counters

This document discusses counters in digital electronics. It begins by defining a counter as a sequential circuit that cycles through a fixed sequence of states, with the states stored in flip-flops. An n-bit counter can cycle through up to 2^n states. Binary counters cycle through all states in ascending or descending order. The design of counters involves drawing a state graph, constructing a state table, deriving K-maps to determine flip-flop inputs, and designing the circuit. Examples are provided to illustrate the design of both synchronous and asynchronous counters using D, T, and JK flip-flops.

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22 views

ECE 301 - Digital Electronics: Counters

This document discusses counters in digital electronics. It begins by defining a counter as a sequential circuit that cycles through a fixed sequence of states, with the states stored in flip-flops. An n-bit counter can cycle through up to 2^n states. Binary counters cycle through all states in ascending or descending order. The design of counters involves drawing a state graph, constructing a state table, deriving K-maps to determine flip-flop inputs, and designing the circuit. Examples are provided to illustrate the design of both synchronous and asynchronous counters using D, T, and JK flip-flops.

Uploaded by

khyatichavda
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 301 Digital Electronics

Counters
(Lecture #20)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6
th
Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Spring 2011 ECE 301 - Digital Electronics 2
Counters

A counter is a sequential circuit (aka. finite


state machine) that cycles through a fixed
sequence of states.

The state of the counter is stored in Flip-Flops.

An n-bit counter

has n Flip-Flops

can cycle through at most 2


n
states.
Spring 2011 ECE 301 - Digital Electronics 3
Counters
00
10
01 11
010 110
000 001 111
011 100 101
2-bit Counter
3-bit Counter
Spring 2011 ECE 301 - Digital Electronics 4
Counters
2-bit Counter
3-bit Counter
00
01
10
using only 3 states
using only 5 states
010
101 011
000
110
Spring 2011 ECE 301 - Digital Electronics 5
Binary Counters

An n-bit binary counter is a counter that cycles


through all 2
n
states in ascending (or
descending) order.
010 110
000 001 111
011 100 101
3-bit Binary Counter
Cycles through all 8 states
in ascending order
Spring 2011 ECE 301 - Digital Electronics 6
Binary Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.


3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.


4.Determine the input equation(s) for each
Flip-Flop.
Spring 2011 ECE 301 - Digital Electronics 7
Binary Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
D
C
D
B
D
A
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Q
+
= D
Characteristic
Equation:
Spring 2011 ECE 301 - Digital Electronics 8
Binary Counters: Design
Example: K-maps (for D FF inputs)
Spring 2011 ECE 301 - Digital Electronics 9
Binary Counters: Design
Example: Circuit Diagram (using D FF)
Spring 2011 ECE 301 - Digital Electronics 10
Binary Counters: Design
Example: State Table (using T FF)
Q
+
= T xor Q
Characteristic
Equation:
Present State Next State FF Inputs
C B A C
+
B
+
A
+
T
C
T
B
T
A
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Excitation Table:
Q Q
+
T
0 0 0
0 1 1
1 0 1
1 1 0
Spring 2011 ECE 301 - Digital Electronics 11
Binary Counters: Design
Example: K-maps (for T FF inputs)
Spring 2011 ECE 301 - Digital Electronics 12
Binary Counters: Design
Example: Circuit Diagram (using T FF)
Spring 2011 ECE 301 - Digital Electronics 13
Binary Up-Down Counters
What constraints must be placed on the U and D control signals?
Spring 2011 ECE 301 - Digital Electronics 14
Binary Up-Down Counters
Spring 2011 ECE 301 - Digital Electronics 15
Loadable Counter with Enable
Spring 2011 ECE 301 - Digital Electronics 16
Counters: Design
1.Draw a state graph that specifies the desired
sequence of the counter.
2.Construct a state table from the state graph.

One Flip-Flop for each bit in the state.


3.Derive a K-map from the state table for each
Flip-Flop input.

Select the type of Flip-Flop to be used.


4.Determine the input equation(s) for each
Flip-Flop.
Spring 2011 ECE 301 - Digital Electronics 17
Counters: Design
Example:
Design the following counter using D Flip-Flops.
Spring 2011 ECE 301 - Digital Electronics 18
Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
D
C
D
B
D
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
D = Q
+
Excitation
Equation:
Spring 2011 ECE 301 - Digital Electronics 19
Counters: Design
Example: K-maps (for D FF inputs)
D
C
D
B
D
A
Spring 2011 ECE 301 - Digital Electronics 20
Counters: Design
Example: Circuit Diagram (using D FF)
Spring 2011 ECE 301 - Digital Electronics 21
Counters: Design
Example:
Design the following counter using T Flip-Flops.
Spring 2011 ECE 301 - Digital Electronics 22
Counters: Design
Example: State Table (using T FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
T
C
T
B
T
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
T = Q xor Q
+
Excitation
Equation:
Spring 2011 ECE 301 - Digital Electronics 23
Counters: Design
Example: K-maps (for T FF inputs)
Spring 2011 ECE 301 - Digital Electronics 24
Counters: Design
Example: K-maps (for T FF inputs)
We could derive T
C
, T
B
, and T
A
directly from the state table,
but it is often more convenient to plot next-state maps
showing C
+
, B
+
, and A
+
as functions of C, B, and A, and then
derive T
C
, T
B
, and T
A
from these maps.
Spring 2011 ECE 301 - Digital Electronics 25
Counters: Design
Example: Circuit Diagram (using T FF)
Spring 2011 26
Counters: Design
Example: Next States (for T FF inputs)
Although the original state table for the counter is not
completely specified, the next states of states 001, 101,
and 110 have been specified in the process of
completing the circuit design
110 101
Spring 2011 ECE 301 - Digital Electronics 27
Counters: Design
Example:
Design the following counter using JK Flip-Flops.
Spring 2011 ECE 301 - Digital Electronics 28
Counters: Design
Example: Using JK Flip-Flops
Excitation Table:
Q Q
+
J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
Spring 2011 ECE 301 - Digital Electronics 29
Counters: Design
Example: State Table (using JK FF)
Present State Next State FF Inputs
C B A C
+
B
+
A
+
J
C
K
C
J
B
K
B
J
A
K
A
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
Spring 2011 ECE 301 - Digital Electronics 30
Counters: Design
Example: K-maps (for JK FF inputs)
Spring 2011 ECE 301 - Digital Electronics 31
Counters: Design
Example: Circuit Diagram (using JK FF)
Spring 2011 ECE 301 - Digital Electronics 32
Questions?

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