Z80 Family

CPU User Manual

User Manual
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This publication is subject to replacement by a later edition. To determine whether a later

edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com

Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Table of Contents
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List of Instructions
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List of Tables
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This user manual describes the architecture and instruction set of the Z80
CPU.

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ZiLOG recommends that the user read and understand everything in this
manual before setting up and using the product. However, we recognize
that users have different styles of learning: some will want to set up and
use their new evaluation kit while they read about it; others will open
these pages only to check on a particular specification. Therefore, we
have designed this manual to be used either as a how to procedural
manual or a reference guide to important data.

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This document is written for ZiLOG customers who are experienced at
working with microprocessors or in writing assembly code or compilers.

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The Z80 CPU Users Manual is divided into four chapters.

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Presents an overview of the Users Manual Architecture, Pin descriptions,
timing and Interrupt Response.

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Presents examples of the Users Manual hardware and software.

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Presents the Users Manual instruction types, addressing modes and
instruction Op Codes.

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Presents an overview of the Users Manual assenbly language, status
indicator flags and the Z80 instructions.

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The following assumptions and conventions are adopted to provide clarity
and ease of use:

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The words set and clear imply that a register bit or a condition contains
the values logical 1 and logical 0, respectively. When either of these
terms is followed by a number, the word logical may not be included, but
it is implied.

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A field of bits within a register is designated as: Register (nn). For
example: PWM_CR (3120). A field of bits within a bus is designated as:
Busnn. For example: PCntl74. A range of similar (whole) registers is
designated as: RegisternRegistern. For example: OPBCS5OPBCS0.

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In this document, the terms LSB and MSB, when appearing in upper case,
mean least significant byte and most significant byte, respectively. The
lowercase forms, msb and lsb, mean least significant bit and most
significant bit, respectively.

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Commands, code lines and fragments, register (and other) mnemonics,
values, equations, and various executable items are distinguished from
general text by the use of the Courier font. This convention is not used
within tables. For example: The STP bit in the CNTR register must be 1.
Where the use of the font is not possible, as in the Index, the name of the
entity is presented in upper case.

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Hexadecimal values are designated by a uppercase H and appear in the
Courier typeface. For example: STAT is set to F8H.

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The use of all uppercase letters designates the names of states and
commands. For example: The receiver can force the SCL line to Low to
force the transmitter into a WAIT state. The bus is considered BUSY after
the Start condition. A START command triggers the processing of the
initialization sequence.

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Initial uppercase letters designate settings, modes, and conditions in
general text. For example: The Slave receiver leaves the data line High. In
Transmit mode, the byte is sent most significant bit first. The Master can
generate a Stop condition to abort the transfer.

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Register access is designated by the following abbreviations:
Designation

Description

Read Only

R/W

Read/Write

Write Only

Unspecified or indeterminate

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The ZiLOG Z80 CPU family of components are fourth-generation
enhanced microprocessors with exceptional computational power. They
offer higher system throughput and more efficient memory utilization
than comparable second- and third-generation microprocessors. The
speed offerings from 620 MHz suit a wide range of applications which
migrate software. The internal registers contain 208 bits of read/write
memory that are accessible to the programmer. These registers include
two sets of six general purpose registers which may be used individually
as either 8-bit registers or as 16-bit register pairs. In addition, there are
two sets of accumulator and flag registers.
The Z80 CPU also contains a Stack Pointer, Program Counter, two index
registers, a REFRESH register, and an INTERRUPT register. The CPU is
easy to incorporate into a system since it requires only a single +5V
power source. All output signals are fully decoded and timed to control
standard memory or peripheral circuits; the Z80 CPU is supported by an
extensive family of peripheral controllers.
Figure 1 illustrates the internal architecture and major elements of the
Z80 CPU.

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The Z80 CPU contains 208 bits of R/W memory that are available to the
programmer. Figure 2 illustrates how this memory is configured to
eighteen 8-bit registers and four 16-bit registers. All Z80 registers are
implemented using static RAM. The registers include two sets of six
general-purpose registers that may be used individually as 8-bit registers
or in pairs as 16-bit registers. There are also two sets of accumulator and
flag registers and six special-purpose registers.

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The program counter holds the 16-bit address of the current instruction
being fetched from memory. The PC is automatically incremented after its
contents have been transferred to the address lines. When a program jump
occurs, the new value is automatically placed in the PC, overriding the
incrementer.

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The stack pointer holds the 16-bit address of the current top of a stack
located anywhere in external system RAM memory. The external stack
memory is organized as a last-in first-out (LIFO) file. Data can be pushed
onto the stack from specific CPU registers or popped off of the stack to
specific CPU registers through the execution of PUSH and POP instructions.
The data popped from the stack is always the last data pushed onto it. The

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stack allows simple implementation of multiple level interrupts, unlimited

subroutine nesting and simplification of many types of data manipulation.

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The two independent index registers hold a 16-bit base address that is
used in indexed addressing modes. In this mode, an index register is used
as a base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify
a displacement from this base. This displacement is specified as a twos
complement signed integer. This mode of addressing greatly simplifies
many types of programs, especially where tables of data are used.

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The Z80 CPU can be operated in a mode where an indirect call to any
memory location can be achieved in response to an interrupt. The I
register is used for this purpose and stores the high order eight bits of the
indirect address while the interrupting device provides the lower eight bits
of the address. This feature allows interrupt routines to be dynamically
located anywhere in memory with minimal access time to the routine.

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The Z80 CPU contains a memory refresh counter, enabling dynamic
memories to be used with the same ease as static memories. Seven bits of
this 8-bit register are automatically incremented after each instruction
fetch. The eighth bit remains as programmed, resulting from an LD R, A
instruction. The data in the refresh counter is sent out on the lower portion
of the address bus along with a refresh control signal while the CPU is
decoding and executing the fetched instruction. This mode of refresh is
transparent to the programmer and does not slow the CPU operation. The
programmer can load the R register for testing purposes, but this register
is normally not used by the programmer. During refresh, the contents of
the I register are placed on the upper eight bits of the address bus.

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The CPU includes two independent 8-bit accumulators and associated 8bit flag registers. The accumulator holds the results of 8-bit arithmetic or
logical operations while the FLAG register indicates specific conditions
for 8-bit or 1 16-bit operations, such as indicating whether or not the
result of an operation is equal to zero. The programmer selects the
accumulator and flag pair with a single exchange instruction so that it is
possible to work with either pair.

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Two matched sets of general-purpose registers, each set containing six 8-bit
registers, may be used individually as 8-bit registers or as 16-bit register
pairs. One set is called BC, DE, and HL while the complementary set is
called BC, DE, and HL. At any one time, the programmer can select either
set of registers to work through a single exchange command for the entire
set. In systems that require fast interrupt response, one set of general-purpose
registers and an ACCUMULATOR/FLAG register may be reserved for handling
this fast routine. One exchange command is executed to switch routines.
This greatly reduces interrupt service time by eliminating the requirement
for saving and retrieving register contents in the external stack during
interrupt or subroutine processing. These general-purpose registers are used
for a wide range of applications. They also simplify programing, specifically
in ROM-based systems where little external read/write memory is available.

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The 8-bit arithmetic and logical instructions of the CPU are executed in
the ALU. Internally, the ALU communicates with the registers and the
external data bus by using the internal data bus. Functions performed by
the ALU include:

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Add
Subtract
Logical AND
Logical OR
Logical Exclusive OR
Compare
Left or Right Shifts or Rotates (Arithmetic and Logical)
Increment
Decrement
Set Bit
Reset Bit
Test bit

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As each instruction is fetched from memory, it is placed in the
INSTRUCTION register and decoded. The control sections performs this
function and then generates and supplies the control signals necessary to
read or write data from or to the registers, control the ALU, and provide
required external control signals.

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The Z80 CPU I/O pins are illustrated in Figure 3 and the function of each
is described in the following paragraphs.

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M1

System
Control

19
20
21
22

MREQ
IORQ
RD
WR

28

RFSH

18

HALT

24

WAIT
CPU
Control

16

INT
NMI

Address
Bus

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23

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BUSACK

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CLK
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A11
A12
A13
A14
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RESET
CPU
Bus
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32
33
34
35
36
37
38
39
40
1
2
3
4
5

14
15
12
8
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9
10
13

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D4
D5
D6
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Address Bus (output, active High, tristate). A15-A0 form a 16-bit address
bus. The Address Bus provides the address for memory data bus
exchanges (up to 64 Kbytes) and for I/O device exchanges.

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Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals
MREQ, IORQ RD, and WR have entered their high-impedance states.
The external circuitry can now control these lines.

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Bus Request (input, active Low). Bus Request has a higher priority than
NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals
MREQ IORQ, RD, and WR to go to a high-impedance state so that other
devices can control these lines. BUSREQ is normally wired-OR and
requires an external pull-up for these applications. Extended BUSREQ
periods due to extensive DMA operations can prevent the CPU from
properly refreshing dynamic RAMS.

''
Data Bus (input/output, active High, tristate). D7D0 constitute an
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+$/7
HALT State (output, active Low). HALT indicates that the CPU has
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maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.

,17
Interrupt Request (input, active Low). Interrupt Request is generated by
I/O devices. The CPU honors a request at the end of the current
instruction if the internal software-controlled interrupt enable flip-flop
(IFF) is enabled. INT is normally wired-OR and requires an external
pull-up for these applications.

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Input/Output Request (output, active Low, tristate). IORQ indicates that
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or write operation. IORQ is also generated concurrently with M1 during
an interrupt acknowledge cycle to indicate that an interrupt response
vector can be placed on the data bus.

0
Machine Cycle One (output, active Low). M1, together with MREQ,
indicates that the current machine cycle is the opcode fetch cycle of an
instruction execution. M1 together with IORQ, indicates an interrupt
acknowledge cycle.

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Memory Request (output, active Low, tristate). MREQ indicates that the
address bus holds a valid address for a memory read of memory write
operation.

10,
Non-Maskable Interrupt (input, negative edge-triggered). NMI has a
higher priority than INT. NMI is always recognized at the end of the
current instruction, independent of the status of the interrupt enable flipflop, and automatically forces the CPU to restart at location 0066H.

5'
Read (output, active Low, tristate). RD indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device or
memory should use this signal to gate data onto the CPU data bus.

5(6(7
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the interrupt enable flip-flop, clears the PC and registers I and R, and sets

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the interrupt status to Mode 0. During reset time, the address and data bus
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full clock cycles before the reset operation is complete.

5)6+
Refresh (output, active Low). RFSH, together with MREQ indicates that
the lower seven bits of the systems address bus can be used as a refresh
address to the systems dynamic memories.

:$,7
WAIT (input, active Low). WAIT communicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. The
CPU continues to enter a WAIT state as long as this signal is active.
Extended WAIT periods can prevent the CPU from properly refreshing
dynamic memory.

:5
Write (output, active Low, tristate). WR indicates that the CPU data bus
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&/.
Clock (input). Single-phase MOS-level clock.

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this line takes priority over the normal interrupt and it can not be disabled
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10

11

13
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data: defs

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high order partial result

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low order partial result

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high order multiplicand

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low order multiplicand

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counter for number of shifts

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30

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(ED)
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80

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82

83

84

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91

92

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98

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23

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SRA

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ED
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Enable Interrupt
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C8

C8

C8

C8

C8

C8

C8

C8

C8

47

40

41

42

43

44

45

46

46

46

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

4F

48

49

4A

48

4C

4D

4E

4E

4E

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C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

57

50

51

52

53

54

55

56

56

56

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

5F

58

59

5A

5B

5C

5D

5E

46

46

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

67

60

61

62

63

64

65

66

66

66

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

6F

68

69

6A

68

6C

6D

6E

6E

6E

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FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

77

70

71

72

73

74

75

76

76

76

DD

DD

C8

C8

C8

C8

C8

CS

C8

C8

C8

78

79

7A

78

7C

7D

7E

46

80

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C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

87

80

81

82

83

84

85

86

86

86

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FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

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8F

88

89

8A

88

8C

8D

8E

8E

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C8

C8

CS

C8

C8

C8

C8

C8

C8

C8

97

90

91

92

93

94

95

96

96

96

DD

FD

C8

C8

C8

C8

CS

C8

C8

C8

C8

C8

9F

98

99

9A

98

90

90

9E

9E

9E

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C8

C8

C8

C6

C8

C8

C8

C8

C8

A7

AO

AI

A2

A3

A4

A5

A6

A6

A6

DD
5

C8

FD

C8

C8

C8

C8

08

C8

C8

C8

C8

C8

AF

A8

A9

AA

AB

AC

AD

AE

AE

AE

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

B7

B0

B1

82

B3

B4

B5

B6

B6

B6

DD
7

C8

DD

C8

C8

C8

C8

C8

C8

C8

C8

C8

BF

B8

89

8A

B8

8C

BD

9E

BE

80

C8

BE

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Set
Bit
SET

SrtDqv

Dqrrq

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

C7

C0

C1

C2

C3

C4

C5

C6

C6

C6

DD
C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

C9

CA

C8

CC

CD

CE

CE

CE

DD
2

FD

C8
CF

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

D7

DO

D1

D2

D3

D4

DS

D6

D6

D6

DD
3

C8

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

C8

DF

D8

09

DA

DS

DC

DD

DE

DE

DE

DD

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

E7

E0

E1

E2

E3

E4

E5

E6

E6

E6

DD
5

C8

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

EF

E8

E9

EA

EB

EC

ED

EE

EE

EE

DD
6

C8

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

F7

FO

F1

F2

F3

F4

FS

F6

F6

F6

DD
7

C8

FD

C8

C8

C8

C8

C8

C8

C8

C8

C8

FF

F8

F9

FA

FB

FC

FD

FE

FE

80

C8

FE

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7DEOH  -XPS &DOO DQG 5HWXUQ *URXS

8qvv

UnCarry
Cond.

Non
Carry

Zero

Non
Zero

Parity Parity Sign

Even Odd
Neg

Sign
Pos

EA
n
n

E2
n
n

FA
n
n

F2
n
n

EC
n
n

E4
n
n

FC
n
n

F4
n
n

JUMP JP

IMMED.
EXT.

nn

C3
n
n

D8
n
n

D2
n
n

CA
n
n

C2
n
n

JUMP JR

RELATIVE

PC+e

18
e-2

38
e-2

30
e-2

28
e-2

20
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Register
INDIR.

(HL)

EB

(IX)

DD
E9

(IY)

FD
E9

nn

CD
n
n

DC
n
n

D4
n
n

CC
n
n

C4
n
n

Reg
B0

CALL

IMMED.
EXT.

Decrement B, Jump RELATIVE

If Non Zero DJNZ

PC+e

Return RE

C9
(SP)
(SP+1)
ED
4D

Return From
INT RETI

REGISTER
INDIR.

10
e-2
D8

D0

C8

C0

E8

E0

F8

F0

ED
45

Return From
Non Maskable
INT RETN

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N, N+1

LD B, 7

: set B register to count of 7

N+2 to N+9

(Perform a sequence of instructions) : loop to be performed 7 times

N+10,N+11

DJNZ -8

N + 12

(Next Instruction)

80

: to jump from N+12 to N+2

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RST 8

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RST 16

0018H DF

RST 24

0020H E7

RST 32

0028H EF

RST 40

0030H F7

RST 48

0038H FF

CALL
Address

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Address of Interrupt
Service Routine

80

Pointer to Interrupt Table,

Register I is Upper Address,
Peripheral Supplies
Lower Address

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(n)
Input
Input IN
Destination

DB
n

Register A
Address

(c)
ED
7B

B
C

ED
48

ED
50

ED
58

ED
60

L
INI - input &
inc HL, Dec B

ED
40

ED
68

Register (HL)
Indir

ED
A2

INIR - INP, Inc HL,

Dec B, repeat IF B0
IND - input & Inc
Dec HL, Dec B

ED
AA

INDR - input, Dec HL,

Dec B, repeat IF B0

80

ED
B2

Block
Input
Commands

ED
BA

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Register
Register Indir.
A B C D E H L (HL)
11OUT
Immed (n) D3
n
.
Reg
(c) ED ED ED ED ED ED ED
Ind.
79 41 49 51 59 61 69
11OUT - output
ED
Block
inc HL, dec B
A3
Output
Command
ED
11OUT - output
B3
dec B, repeat if B0
11OUT - output
ED
dec HL and B
AB
ED
11OUTDR - output, dec
BB
HL and B, repeat IF B0
Port
Destination
Address

7DEOH  0LVFHOODQHRXV &38 &RQWURO

NOP
HALT
Disable INT (EI)
Enable INT (EI)
Set INT mode 0
IM0
Set INT mode 1
IM1
Set INT mode 2
IM2

80

00
76
F3
FB
ED
46
ED
56
ED
5E

8080A mode
Call to location 0038H
indirect call using register I and B
bits from INTER device as a pointer

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Add/Subtract

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Zero Flag

Sign Flag

Not Used

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1000

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0110

1001

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1110

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SUM

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A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs

No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs

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