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This document provides an overview of the objectives and syllabus for the course CS608 Computer Architecture. The objectives are to: 1) understand basic architecture concepts, 2) expose the design of the ALU, 3) cover execution methods and pipelining, 4) understand memory unit design and usage, and 5) cover interfacing methods and devices. The syllabus covers five units - instruction set architecture, arithmetic/logic unit, data path and control, memory systems, and I/O and interfaces. Textbooks and references are also listed.

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104 views

Text Books

This document provides an overview of the objectives and syllabus for the course CS608 Computer Architecture. The objectives are to: 1) understand basic architecture concepts, 2) expose the design of the ALU, 3) cover execution methods and pipelining, 4) understand memory unit design and usage, and 5) cover interfacing methods and devices. The syllabus covers five units - instruction set architecture, arithmetic/logic unit, data path and control, memory systems, and I/O and interfaces. Textbooks and references are also listed.

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Anonymous 8pCXXs
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© Attribution Non-Commercial (BY-NC)
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CS608 COMPUTER ARCHITECTURE AIM To contribute the knowledge about the computer architecture and the working nature

of the computer parts. OBJECTIVES 1. 2. 3. 4. !. To make students understand the basic concept of architecture. To expose the design procedure of ALU. To expose the execution methods and the pipelining concept. To make students understand the design and usage of memor unit. To expose the interfacing methods and de"ices. 9

SYLLABUS: AS PER ANNA UNIVERSITY, TIRUNELVELI-REGULATION 2008 UNIT- I INSTRUCTION SET ARCHITECTURE #ntroduction to computer architecture $ %e"iew of digital design & #nstructions and addressing & procedures and data & assembl language programs & instruction set "ariations. UNIT-II ARITHMETIC/LOGIC UNIT 9 'umber representation & design of adders & design of simple ALUs & design of (ultipliers and di"iders & design of floating point arithmetic unit. UNIT-III DATA PATH AND CONTROL 9 #nstruction execution steps & control unit s nthesis & microprogramming & pipelining & pipeline performance. UNIT-IV MEMORY SYSTEM 9 (ain (emor concepts & t pes of memor & cache memor organi)ation & secondar storage & "irtual memor & paging. UNITV I/O AND INTER ACES 9 #*+ de"ices & #*+ programming & polling & interrupts & ,(A & buses & links & interfacing$context switching & threads and multithreading. TOTAL: !" PERIODS

TE#T BOO$S 1. -arl .amacher/ 0"onko 1ranesic and 2afwat 0ak / 3-omputer +rgani)ation4/ 5ifth 6dition/ Tata (c7raw .ill/ 2882. 2. 9. :arhami/ 3-omputer Architecture4/ +xford Uni"ersit :ress/ 288!. ADDITIONAL TE#T BOO$ 1. ;ohn.:..a es/ 3-omputer architecture and organi)ation4/ Third 6dition/ (c7raw hill international edition/ 1<<=. 2. (.(orris (ano/ 3-omputer s stem architecture4/ Third edition/ :.# p"t. Ltd/ 2883. RE ERENCES 1. ,a"id A. :atterson and ;ohn L. .enness / 3-omputer +rgani)ation and ,esign> The .ardware*2oftware interface4/ A%( 6dition/ 6lse"ier/ 2818. 2. ?illiam 2tallings/ 3-omputer +rgani)ation and Architecture & ,esigning for :erformance4/ 2e"enth 6dition/ :earson 6ducation/ 288@.

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