1.

Realization of Logic Gates using Gate

Level Modeling
module lg_gate_primitive(
Input

Output

and

or

~A

~b

nand

nor

xor

Xnor

input a,b,
output [7:0] y
);
and

A1 (y[0],a,b);

or

A2 (y[1],a,b);

not

A3 (y[2],a);

not

A4 (y[3],b);

nand A5 (y[4],a,b);
nor
xor

A6 (y[5],a,b);
A7 (y[6],a,b);

xnor A8 (y[7],a,b);
endmodule

7408N_VHDL
7404N_VHDL
7432N_VHDL
U6A
U3A
U2A
U9A
7404N_VHDL

a
b
a
b

y[0]=ab
AND Gate
y[1]=a+b

a
b

y[2]=a'

a
b

OR Gate

a
NOT Gate
b

y[3]=b'
NOT Gate

a
b

7400
y[4]=(ab)'
NAND Gate
y[5]=(a+b)'
NOR Gate
y[6]=ab'+a'b
XOR Gate

a
b

y[7]=ab+a'b'
XNOR Gate

74AC1

2. Realization of Half Adder using Gate

Level Modeling

module ha_gate_primitive(

input a,b,
output sum,carry
);
xor

A1

and A2
endmodule

(sum,a,b);
(carry,a,b);

Input

Output

Sum

Carry

7408N_VHDL
U8A
74AC11002N_VHDL
U3A

a
b

Sum=ab'+a'b
Carry=ab
HALF ADDER

3. Realization of Full Adder using Gate

Level Modeling
module fa_gate_primitives(

input a,b,cin,
output s,cout

Input

Output

c in

c out

);
wire

z1,z2,z3;
7408N_VHDL
U2A

xor XOR1 (z1,a,b);

xor XOR2 (s,cin,z1);

7408N_VHDL
7486D_VHDL
U4A
U1A
U5A 7432N_VHDL U3A

and AND1 (z2,a,b);

7486N_VHDL

and AND2 (z3,cin,z1);

or

OR1

endmodule

(cout,z2,z3);
a
b
cin

z1
Sum
z2
Cout
z3
FULL ADDER

4. Realization of 2:1 MUX using Gate

Level Modeling

module mux2to1_gp(

Selict
line

Input

Output

W1

W0

input [1:0] w,
input s,
input f
);

7400N_VHDL
7432N_VHDL
U6A
U1A
U3A 7404N_VHDL
U2A
7400N_VHDL

wire

z1,z2,z3;

not A1 (z1,s);
and A2 (z2,w[0],z1);

w[0]

z2

and A3 (z3,w[1],s);
or

A4 (f,z2,z3);

endmodule

z1

w[1]

z3
2:1 MUX

5. Realization of Logic Gates using Data

Flow Modeling
module lg_data_flow(
Input

Output

and

or

~A

~b

nand

nor

xor

Xnor

input a,b,
output [7:0] y
);
assign y[0]=a&b;
7408N_VHDL
7404N_VHDL
7432N_VHDL
U6A
U3A
U2A
U9A
7404N_VHDL

assign y[1]=a|b;
assign y[2]=~a;
assign y[3]=~b;
assign y[4]=~(a&b);
assign y[5]=~(a|b);

a
b
a
b

assign y[6]=a^b;
assign y[7]=a~^b;

endmodule

y[0]=ab
AND Gate
y[1]=a+b

a
b

y[2]=a'

a
b

OR Gate

a
NOT Gate
b

y[3]=b'
NOT Gate

a
b

7400
y[4]=(ab)'
NAND Gate
y[5]=(a+b)'
NOR Gate
y[6]=ab'+a'b
XOR Gate

a
b

y[7]=ab+a'b'
XNOR Gate

74AC1

6. Realization of Full Adder using assign

and logical operators
module fa_df_logical_operators(

input a,b,cin,
output s,cout
);
assign s = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b ));
endmodule

Input

Output

c in

c out

U2A
7408N_VHDL
7486D_VHDL
U4A
U1A
U5A 7432N_VHDL U3A
7486N_VHDL

a
b
cin

z1
Sum
z2
Cout
z3
FULL ADDER

7. Realization of binary to grey code

converter using assign
statements
Binary code

module binary_grey(
input [3:0] b,
output [3:0] g);
assign g[3] = b[3];
assign g[2] = b[3] ^ b[2];
assign g[1] = b[2] ^ b[1];
assign g[0] = b[1] ^ b[0];

Grey code

B
3

B
2

G0

74AC11002N_VHDL
U2A
74AC11002N_VHDL
U1A
74AC11002N_VHDL
U8A

endmodule
b[3]
b[2]
b[1]
b[0]

g[3]
g[2]
g[1]
g[0]

BINARY TO GREY CODE CONVERTER

8. Realization of 2:1 MUX using

conditional operator

module mux2to1_conditional_operators(

Selict line

W
1

W0

output f
);
7400N_VHDL
7432N_VHDL
U6A
U1A
U3A 7404N_VHDL
U2A
7400N_VHDL

endmodule

w[0]
s

w[1]
2:1 MUX

Output

input s,w0,w1,

assign f = s? w1 : w0;

Input

9. Realization of 4:1 MUX using

conditional operator
Selict
lines

module mux4to1_conditional_operator(
input [1:0] s,
input [3:0] w,
output f
);
assign f=s[1]?(s[0]? w[3] : w[2]):(s[0]?w[1]:w[0]);
endmodule

Input

Output

S
1

S0

W3

W2

W1

W0

10. Realization of 4:1 MUX using Gate

Level Modeling
module mux4to1_gp(
input s1,s0,

U4A
7411D_VHDL
7404N_VHDL
7411D_VHDL
U7A
U8A
7432N_VHDL
U9A
U5A
7411D_VHDL
U10A
7411D_VHDL

input [3:0] w,
output f
);

7404N_VHDL
U11A

wire z1,z2,z3,z4,z5,z6;
not A1 (z1,s0);
not A2 (z2,s1);
and A3 (z3,w[0],z1,z2);

w[0]
s[0]

and A6 (z6,w[3],s1,s0);
or A7 (f,z3,z4,z5,z6);
endmodule

z1

w[1]

z4
f

w[2]

and A4 (z4,w[1],z2,s0);
and A5 (z5,w[2],s1,z1);

z3

s[1]

z2

z5

w[3]
z6

11. Realization of Full Adder using two

Half Adders
module fa_using_ha(
Input

input a,b,cin,

output s,cout
);
ha_gate_primitive

HA1 (a,b,z2,z1);

ha_gate_primitive

HA2 (cin,z2,s,z3);

Output

c in

c out

or OR1 (cout,z1,z3);

7432N_VHDL
U5A

endmodule

module ha_gate_primitive(
input a,b,
output sum,carry

xor

A1

(sum,a,b);

and

A2

(carry,a,b);

cout
HA1

);

endmodule

z1

z2

z3
HA2

cin

FULL ADDER

12. Realization of 16:1 MUX using 4:1

MUX
module mux16to1_using_4to1(
input [3:0] s,
input [0:15] w,

W[0]
W[1]
W[2]

m[0]

16:1 MUX

4:1 MUX

W[3]

output f
);
wire [0:3]m;
mux4to1 MUX1 (s[3:2],w[0:3],m[0]);

W[4]
W[5]
W[6]

m[1]
4:1 MUX

W[7]

4:1 MUX

mux4to1 MUX2 (s[3:2],w[4:7],m[1]);

W[8]

mux4to1 MUX3 (s[3:2],w[8:11],m[2]);

mux4to1 MUX4 (s[3:2],w[12:15],m[3]);

W[9]
W[10]

m[2]
4:1 MUX

W[11]

mux4to1 MUX5 (s[1:0],m[0:3],f);

endmodule

W[12]
W[13]
W[14]

m[3]
4:1 MUX

W[15]

module mux4to1(
input [1:0] s,
input [3:0] w,
output f
);
assign f= s[1]? (s[0]? w[3] : w[2]) : (s[0]? w[1] : w[0]);
endmodule

S[3] S[2]

S[1] S[0]

13. Realization of 4 bit Parallel Adder

using Full Adder

module pa(
input [3:0] fa,fb,
input fcin,
output [3:0] fsum,
output fcout
);
wire [3:1]ft;
fa FA1 (.a(fa[0]),.b(fb[0]),.cin(fcin),.s(fsum[0]),.cout(ft[1]));
fa FA2 (.a(fa[1]),.b(fb[1]),.cin(ft[1]),.s(fsum[1]),.cout(ft[2]));
fa FA3 (.a(fa[2]),.b(fb[2]),.cin(ft[2]),.s(fsum[2]),.cout(ft[3]));
fa FA4 (fa[3],fb[3],ft[3],fsum[3],fcout);
endmodule

module fa (
input a,b,cin,
output s,cout
);
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);
endmodule

FB[3] FA[3]

A
FA4

FB[2] FA[2]

Cout S

FA3

Cin

A
FA2

Cin

Cout S
FT[3]

FCout FSum[3]

FB[1] FA[1]

B
Cin

Cout S
FT[2]

FSum[2]

FB[0] FA[0]

FA1

Cin

FCin

Cout S
FT[1]

FSum[1]

FSum[0]

PARALLEL ADDER

14. Realization of 1:4 DEMUX with active

low output
module demux1to4(

input s0,s1,w,
output [3:0] y
);
wire z1,z2;

7410N_VHDL
U10A
7404N_VHD
U9A
7410N_VHDL
7410N_VHDL
U4A
U8A
7410N_VHDL
U11A
7404N_V
U7A

assign z1=~s1;
assign z2=~s0;
assign y[0]=w&z1&z2;
assign y[1]=w&z1&s0;

assign y[2]=w&s1&z2;
assign y[3]=w&s1&s0;
endmodule

s1
s0

y[0]

z1

y[1]
y[2]

z2
y[3]
1:4 DEMUX

15. Test Bench for Half Adder

module stimulus;
reg a,b;
wire sum,carry;
ha uut (.a(a),.b(b),.sum(sum),.carry(carry));
initial
begin
$monitor($time," a=%b b=%b Sum=%b Carry=%b",a,b,sum,carry);
end
initial
begin
a=0 ; b=0;
#2 a=0 ; b=1;
#2 a=1 ; b=0;
#2 a=1 ; b=1;
#10 $stop;
end
endmodule

module ha(
input a,b,
output sum,carry);
xor

A1

(sum,a,b);

and

A2

(carry,a,b);

endmodule

7408N_VHDL
U8A
74AC11002N_VHDL
U3A

Input

a
b

Sum=ab'+a'b
Carry=ab
HALF ADDER

Output

Sum

Carry

16. Test Bench for Parallel Adder

module stimulus;
reg [3:0] fa,fb;
reg fcin;
wire [3:0] fsum;
wire fcout;
pa uut (.fa(fa),.fb(fb),.fcin(fcin),.fsum(fsum),.fcout(fcout));
initial
begin
$monitor($time,"A=%b , B=%b , Cin=%b , Sum=%b , Carry=%b",fa,fb,fcin,fsum
,fcout );
end

initial
begin
fa=0 ; fb=0 ; fcin=0;
#1 fa=4'b0101 ; fb=4'b1011 ; fcin=1;

FB[3] FA[3]

FB[2] FA[2]

FB[1] FA[1]

FB[0] FA[0]

#1 fa=4'b0100 ; fb=4'b1100 ; fcin=0;

#1 fa=4'b0011 ; fb=4'b1000 ; fcin=0;
#1 fa=4'b0010 ; fb=4'b1111 ; fcin=0;
#1 fa=4'b1010 ; fb=4'b0101 ; fcin=1;
#1 fa=4'b1110 ; fb=4'b0001 ; fcin=0;
#1 fa=4'b10001 ; fb=4'b0110 ; fcin=1;
#10 $finish;
end
endmodule

FA4

FA3

Cin

Cout S

Cout S
FT[3]

FCout FSum[3]

FA2

Cin

Cin

Cout S
FT[2]

FSum[2]

FA1

Cin

Cout S
FT[1]

FSum[1]

PARALLEL ADDER

FSum[0]

FCin

module pa(
input [3:0] fa,fb,
input fcin,
output [3:0] fsum,
output fcout
);
wire [3:1]ft;
fa fulladder1 (.a(fa[0]),.b(fb[0]),.cin(fcin),.s(fsum[0]),.cout(ft[1]));
fa fulladder 2 (.a(fa[1]),.b(fb[1]),.cin(ft[1]),.s(fsum[1]),.cout(ft[2]));
fa fulladder 3 (.a(fa[2]),.b(fb[2]),.cin(ft[2]),.s(fsum[2]),.cout(ft[3]));
fa fulladder4 (fa[3],fb[3],ft[3],fsum[3],fcout);
endmodule

module fa (
input a,b,cin,
output s,cout
);
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(a&cin);
endmodule

17. Test Bench for 4:1 MUX

module stimulus;
reg [1:0] s;
reg [3:0] w;
wire f;
mux4to1 uut(.s(s),.w(w),.f(f));
initial
begin
$monitor($time, "S=%b , W=%b , f=%b",s,w,f);
end

initial

Selict
lines

begin
s = 0 ; w = 0;
#1 s=2'b00 ; w=4'b0001;
#1 s=2'b00 ; w=4'b0000;
#1 s=2'b01 ; w=4'b0010;

Input

Output

S
1

S0

W3

W2

W1

W0

#1 s=2'b01 ; w=4'b0000;
#1 s=2'b10 ; w=4'b0100;
#1 s=2'b10 ; w=4'b0000;
#1 s=2'b11 ; w=4'b1000;
#1 s=2'b11 ; w=4'b0000;
#10 $stop;
end
endmodule

module mux4to1 (
input [1:0] s,
input [3:0] w,
output f
);
assign f= s[1]? (s[0]? w[3] : w[2]) : (s[0]? w[1] : w[0]);
endmodule

18. Test Bench for 16:1 MUX

module stimulus;
reg [3:0] s;
reg [0:15] w;
wire f;
mux16to1_using_4to1 uut (.s(s),.w(w),.f(f));
initial
begin
$monitor($time,"S=%b , w=%b , f=%b",s,w,f);
end
initial
begin
s = 0 ; w = 0;
#2 s=4'b1001 ; w=7521;
#1 s=4'b0100 ; w=12501;
#2 s=4'b1010 ; w=25510;
#3 s=4'b0010 ; w=00264;
#10 $finish;
end
endmodule

W[0]

module mux16to1_using_4to1(
input [3:0] s,

W[1]
W[2]

m[0]

16:1 MUX

4:1 MUX

W[3]

input [0:15] w,
output f);
wire [0:3]m;
mux4to1 MUX1 (s[3:2],w[0:3],m[0]);

W[4]
W[5]
W[6]

m[1]
4:1 MUX

W[7]

mux4to1 MUX2 (s[3:2],w[4:7],m[1]);

4:1 MUX

mux4to1 MUX3 (s[3:2],w[8:11],m[2]);

W[8]

mux4to1 MUX4 (s[3:2],w[12:15],m[3]);

W[9]

mux4to1 MUX5 (s[1:0],m[0:3],f);

W[10]

m[2]
4:1 MUX

W[11]

endmodule
W[12]
W[13]

module mux4to1 (

W[14]

m[3]
4:1 MUX

W[15]

input [1:0] s,
input [3:0] w,

S[3] S[2]

output f);
assign f= s[1]? (s[0]? w[3] : w[2]) : (s[0]? w[1] : w[0]);
endmodule

S[1] S[0]

19. 1:4 DEMUX using case statements

module demux1to4_case(
input a,b,en,
output reg [3:0] z
);
always @(a,b,en)
case({en,a,b})
3'b100: z=4'b1110;
3'b101: z=4'b1101;
3'b110: z=4'b1011;
3'b111: z=4'b0111;
default:z=4'b1111;
endcase
endmodule

20. 2:4 Decoder using case statements

module decoder_case(
input [0:1] w,
input en,
output reg [0:3] y
);

always@(w,en)
case({en,w})
3'b100:y=4'b1000;
3'b101:y=4'b0100;
3'b110:y=4'b0010;
3'b111:y=4'b0001;
default:y=4'b0000;
endcase

endmodule

21. 2:4 Decoder using if else and case

statements
module decoder_ifelse_n_case(
input en,
input [0:1] w,
output reg [0:3] y
);
always@(w,en)
begin
if(en==0)
y=4'b0;
else
case(w)
0:y=4'b1000;
1:y=4'b0100;
2:y=4'b0010;
3:y=4'b0001;
default:y=4'b0000;
endcase
end
endmodule

22. 3 bit ALU using case statements

module alu(opode, a,b, res);
input [2:0] opode;
input [3:0] a,b;
output [3:0] res;
reg [3:0] res;
always@(a,b,opode)
case(opode)
0:res=0;
1:res=b-a;
2:res=a-b;
3:res=a+b;
4:res=a^b;
5:res=a|b;
6:res=a&b;
7:res=4'b1111;
endcase
endmodule