The document describes the steps to configure and implement scan/test logic in a design including setting up scan/test logic configuration, performing design rule checks, identifying scan cells, inserting the scan/test logic, and writing out the netlist and setup files.
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DFT Insertion Flow
The document describes the steps to configure and implement scan/test logic in a design including setting up scan/test logic configuration, performing design rule checks, identifying scan cells, inserting the scan/test logic, and writing out the netlist and setup files.