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Lab 3 Solutions

This document contains code for several Verilog modules: 1) A 16-to-1 multiplexer module that selects one of 16 inputs using a 4-bit select line. 2) An 8-bit adder module that adds two 8-bit operands and an optional carry input. 3) A single-bit adder module that performs addition on two 1-bit inputs and a carry input. 4) A CPU module that performs various operations like addition, subtraction, logical operations on two 8-bit operands based on a 4-bit select line. It outputs the result and flags for overflow and half carry.

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32 views

Lab 3 Solutions

This document contains code for several Verilog modules: 1) A 16-to-1 multiplexer module that selects one of 16 inputs using a 4-bit select line. 2) An 8-bit adder module that adds two 8-bit operands and an optional carry input. 3) A single-bit adder module that performs addition on two 1-bit inputs and a carry input. 4) A CPU module that performs various operations like addition, subtraction, logical operations on two 8-bit operands based on a 4-bit select line. It outputs the result and flags for overflow and half carry.

Uploaded by

dubstepo
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab 3 solutions Task 1 Solution

module mux16to1(mux_in,select,mux_out); input [15:0]mux_in; input [3:0]select; output mux_out; reg mux_out; always @ (mux_in or select) begin case(select) 4'd0: mux_out = mux_in[0]; 4'd1: mux_out = mux_in[1]; 4'd2: mux_out = mux_in[2]; 4'd3: mux_out = mux_in[3]; 4'd4: mux_out = mux_in[4]; 4'd5: mux_out = mux_in[5]; 4'd6: mux_out = mux_in[6]; 4'd7: mux_out = mux_in[7]; 4'd8: mux_out = mux_in[8]; 4'd9: mux_out = mux_in[9]; 4'd10: mux_out = mux_in[10]; 4'd11: mux_out = mux_in[11]; 4'd12: mux_out = mux_in[12]; 4'd13: mux_out = mux_in[13]; 4'd14: mux_out = mux_in[14]; 4'd15: mux_out = mux_in[15]; endcase end endmodule

Task 2
module adder8bit(oprnd_a,oprnd_b,crryin,sum,crryout); input [7:0]oprnd_a,oprnd_b; input crryin; output [7:0]sum; output crryout; reg [7:0]sum; reg crryout; always @(oprnd_a or oprnd_b or crryin) begin {crryout,sum} = oprnd_a + oprnd_b + crryin; end endmodule

TASK 3
module onebitadd (a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a ^ b ^ cin; assign cout = (a & b) | (cin & (a ^ b)); endmodule

module cpu(oprnd_a,oprnd_b,cpu_out,halfcarry,overflow,select); input [7:0]oprnd_a,oprnd_b; input [3:0]select; output reg [7:0]cpu_out; output reg overflow,halfcarry; wire [7:0]xorout,c,add_subout; wire c_in; assign xorout[0] = oprnd_b[0] ^ ( select[3] & ~select[2] & select [1] // assumption ---- select = 1010 means binary subtraction assign xorout[1] = oprnd_b[1] ^ ( select[3] & ~select[2] & select [1] assign xorout[2] = oprnd_b[2] ^ ( select[3] & ~select[2] & select [1] assign xorout[3] = oprnd_b[3] ^ ( select[3] & ~select[2] & select [1] assign xorout[4] = oprnd_b[4] ^ ( select[3] & ~select[2] & select [1] assign xorout[5] = oprnd_b[5] ^ ( select[3] & ~select[2] & select [1] assign xorout[6] = oprnd_b[6] ^ ( select[3] & ~select[2] & select [1] assign xorout[7] = oprnd_b[7] ^ ( select[3] & ~select[2] & select [1] assign c_in = (select[3] & ~ select[2] & select [1] & ~ select[0]); onebitadd inst1(oprnd_a[0],xorout[0],c_in,add_subout[0],c[0]); onebitadd inst2(oprnd_a[1],xorout[1],c[0],add_subout[1],c[1]); onebitadd inst3(oprnd_a[2],xorout[2],c[1],add_subout[2],c[2]); onebitadd inst4(oprnd_a[3],xorout[3],c[2],add_subout[3],c[3]); onebitadd inst5(oprnd_a[4],xorout[4],c[3],add_subout[4],c[4]); onebitadd inst6(oprnd_a[5],xorout[5],c[4],add_subout[5],c[5]); onebitadd inst7(oprnd_a[6],xorout[6],c[5],add_subout[6],c[6]); onebitadd inst8(oprnd_a[7],xorout[7],c[6],add_subout[7],c[7]); & ~ select[0]); & & & & & & & ~ ~ ~ ~ ~ ~ ~ select[0]); select[0]); select[0]); select[0]); select[0]); select[0]); select[0]);

always @(oprnd_a or oprnd_b or select) begin case(select) 4'd0: cpu_out = oprnd_a >> 1; //right shift by 1 4'd1: cpu_out = oprnd_a << 1; //left shift by 1 4'd2: cpu_out = oprnd_b >> 1; //right shift the operand b by 1 4'd3: cpu_out = oprnd_b << 1; //left shift the operand b by 1 4'd4: cpu_out = oprnd_a & oprnd_b; // 'AND'ing 4'd5: cpu_out = oprnd_a | oprnd_b; // 'OR'ing 4'd6: cpu_out = oprnd_a ^ oprnd_b; // 'XOR'ing 4'd7: // BCD error detection and no correction begin cpu_out[7:0] = add_subout[7:0]; if ( (add_subout[3:0]> 4'b1001) || c[3] ) // checking invalid output or half carry halfcarry = 1; end 4'd8: //BCD error detection and correction begin if ( (add_subout[3:0]> 4'b1001) || c[3] ) begin halfcarry = 1; cpu_out = add_subout + 4'd6;

end end 4'd9: {overflow,cpu_out} = {c[7],add_subout}; //unsigned addition with overflow 4'd10:cpu_out = add_subout; // 2s complement subtraction endcase end endmodule

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