PACKAGING

IC Packaging
Purposes
1) Electricalconnections
Signals Powerandground

2) Aidsheatdissipation
Increaseeffectivesurfaceareaforincreasedconvection HeatconductionintoPCboard

3) PhysicalprotectionforIC
e.g.,againstbreakage

4) Environmentalprotection
Hermetic(airtight)seal e.g.,againstcorrosionormoisture

EEC116,Winter2010,B.Baas

Rents Rule
Empiricalformula P=KG P=numberofinput/outputconnections(pins) K=averagenumberofI/Ospergate G=numberofgates =empiricallyfoundparameterthatvariesaccordingto application;generallybetween0.1and0.7
Computer(chip) Computer(board) Staticmemory
EEC116,Winter2010,B.Baas

K 1.4 82 6
3

0.63 0.25 0.12

Package Metrics
Electrical
Lowcapacitance Lowinductance Lowresistance

Mechanical
Reliableacrosstemperaturevariations(thermalexpansion matching)

Thermal
Lowthermalresistancetogettheheatout

Economical(cost)
Purchaseofpackage Assembly(chipandboardassembly) System(heatremovalequipmentincluded)
EEC116,Winter2010,B.Baas
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Package Materials
Plastic
Lowcost Typicallyrequiresacustomdesignedpackage

Ceramic
Betterheattransfercharacteristics Generallymorereliable Morelikelyanofftheshelfpartcanbeused
Goodforresearchandprototyping

EEC116,Winter2010,B.Baas

Interconnection Levels
Multiplelevelsof packaging
Easeofhandling Reuseofintermediatesized modules(e.g.,DRAM memorystick)
Useinmultipleproducts Upgradeableinfield Repairableinfield

system printed circuit board(PCB) package chip

EEC116,Winter2010,B.Baas

Solder
Solderistheuniversalelectricalglue
tinandleadalloy:50/50%,63/37%Sn/Pb eutecticmixture lowmeltingtemperature:183Cor361.4Fforeutectic goodelectricalconductivity

Largeeffortsnowunderwaytoeliminateorreduce theuseoflead
RoHS RestrictionofHazardousSubstancesDirective Manyreplacementsavailable
TypicalonesuseTin,Silver,Copper;maybeBismuth,Indium, Zinc,Antimony

EEC116,Winter2010,B.Baas

PC Board

EEC116,Winter2010,B.Baas

Source: J-Machine, Dally

PC Board

iPhone 3GS, AppleInsider, June 19, 2009

PC Board Stack With Host Computer

EEC116,Winter2010,B.Baas

Source: J-Machine, Dally

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System
JMachine BuiltatMITand Stanfordintheearly 1990s 1024processors

EEC116,Winter2010,B.Baas

Source: J-Machine, Dally

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IBM Blue Gene/L

Thefastestsupercomputerintheworldisa131,072 processorBlueGenemachine

EEC116,Winter2010,B.Baas

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IBM Blue Gene/L

Thefastestsupercomputerintheworldisa131,072 processorBlueGenemachine

EEC116,Winter2010,B.Baas

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Chip to Package Connections

1) Wirebonding
dieattached goldoraluminumwires oneatatime notentirelyrepeatable Electricalcharacteristics:
R:low C:low L:~1nH/mm

EEC116,Winter2010,B.Baas

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Bonding Techniques
Wire Bonding

Substrate Die Pad

Lead Frame

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Wire Bonds
Optical microscope viewofbond wiresforatwo padpackage

EEC116,Winter2010,B.Baas

Source: Assurance Technology

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Wire Bonds
SEMviewof bondwiresfor atwopad package

EEC116,Winter2010,B.Baas

Source: Assurance Technology

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Wire Bonds
SEMviewofa singlebond wire attachment

EEC116,Winter2010,B.Baas

Source: Assurance Technology

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Wire Bonds
Goldwirebond onaluminum diepad

EEC116,Winter2010,B.Baas

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Source: SEM Lab, Inc.

Wire Bonding Machine

Wirebondingmachine

EEC116,Winter2010,B.Baas

Source: TWI, Ltd.

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Chip to Package Connections

2) Tapeautomatedbonding(TAB)
Dieattachedtometalleadframeprintedonpolymerfilm usingsolderbumps Tapethenconnectedtopackage Fastandparalleloperation Lowerelectricalparasitics (R,L,C)

EEC116,Winter2010,B.Baas

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Tape-Automated Bonding (TAB)

Sprocket hole Film + Pattern Test pads Lead frame Die Solder Bump

Substrate (b) Die attachment using solder bumps.

Polymer film (a) Polymer Tape with imprinted wiring pattern.

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Tape-Automated Bonding (TAB)

EEC116,Winter2010,B.Baas Source: Computer Desktop Encyclopedia

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Chip to Package Connections

3) Flipchipsolderbump
chipplacedfacedowninpackage connectedwithsolderbumps verylowparasitics allowsareapads
padscancoverchipareaandare notlimitedtochipperiphery

EEC116,Winter2010,B.Baas

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Flip-Chip Bonding

Die Solder bumps Interconnect layers

Substrate

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Package to Board Connections 1) Through Hole

Classicapproach Holesdrilledandplatedwithcopper Soldering
Chipsplacedinsideholes Bottomofboardpassedthroughamoltensolderwave

EEC116,Winter2010,B.Baas

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2) Surface Mount Technology (SMT)

MorewiringroominsidePCboard Reducedspacebetweenpackageleads Chipsonbothsidesofboard StrongerPCboard Soldering
Solderpasteapplied Heatsuppliedbyintenseinfraredlight,heatedair,

Package to Board Connections

EEC116,Winter2010,B.Baas

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Package-to-Board Interconnect

(a) Through-Hole Mounting

(b) Surface Mount

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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SMT Leads
a) Gullwing SMTpackageleads
Solderingissues
Ex: Thin Small Outline Package Type II (TSOP Type II)

EEC116,Winter2010,B.Baas

http://www.twyman.org.uk/PCB-Techniques/ 29

SMT Leads
b) JLead SMTpackageleads
Manypackagetypesavailable Lessboardspacethangullwing
Ex: Small Outline J-lead (SOJ)

EEC116,Winter2010,B.Baas

http://www.twyman.org.uk/PCB-Techniques/ 30 http://www.ljmu.ac.uk/GERI/VERBONDS.htm

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SMT leads
c) SolderBalls
Similartoflipchipbutatpackagetoboardlevel Verylowparasitics ExampleBGAsolderball (withhighlightedcrack)

EEC116,Winter2010,B.Baas

http://www.calce.umd.edu/general/Facilities/sem.htm

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Package Examples

Through hole

Surface mount

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Package Types DIP Dual In-Line Package

Oneoftheoldestpackagingtechnologies Lowperformance 4864pinpackagesarehuge Cheapandabundant Plasticandceramic

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html http://www.tms.org/pubs/journals/JOM/9903/Frear-9903.html http://www.supertex.com/packaging.html 33 http://www.arlabs.com/help.htm http://en.wikipedia.org/wiki/Dual_in-line_package

Package Types ZIP Zig-Zag In-Line Package

Notverycommon

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html 34

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Package Types SOP Small Outline Package

SOPincludesalargefamilyofpackages
SOIC SmallOutlineIntegratedCircuit SSOP ShrinkSmallOutlinePackage QSOP QuartersizeSmallOutlinePackage TSSOP ThinShrinkSmallOutlinePackage MSOP MiniSmallOutlinePackage

EEC116,Winter2010,B.Baas

http://www.carsem.com/services/package.php http://www.mameworld.net/gurudumps/MyStuff/packages.html 35

Package Types TSOP Thin Small Outline Package

Oneofthesmallestpackagesavailable TypeI leadsonshortsides

TypeII leadsonlongsides

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html http://www.national.com/packaging/dual.html

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Package Types QFP Quad Flat Package

Commoninmodernelectronics

TQFP ThinQuadFlatPackage
Typicalthickness1.4mm

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html 37 http://www.carsem.com/services/package.php

Package Types SOJ Small Outline J-lead

J leadsontwosides

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html http://www.national.com/packaging/dual.html 38 http://www.asetwn.com.tw/content/2-1-2.html http://www.toshiba.co.jp/tech/pat/ip-disclosure/p2538717.htm

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Package Types PLCC Plastic Leaded Chip Carrier

AlsocalledQFJ QuadFlatJlead Commoninmanyproducts

PLCC in socket
http://www.mameworld.net/gurudumps/MyStuff/packages.html http://www.arlabs.com/help.htm 39 http://www.globalchipmaterials.com/visitors/products_visitors_acp_plcc.htm http://www.statschippac.com/en-US/STATSChipPAC/IntegratedServices/Packaging/LeadFrame/plcc.htm http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier

EEC116,Winter2010,B.Baas

Package Types PGA Pin Grid Array Package

Materialthemainbodyconsists ofcofiringmultilayeralumina ceramics,andpinterminalsmade ofanalloyofiron,nickel,and cobaltareattachedwithsilver brazingtothemainbody. 400+pinspossible Cavityup Cavitydown

EEC116,Winter2010,B.Baas

http://www.ngkntk.co.jp/english/product/semi/ic-ceramics/index.html 40 http://www.ntktech.com/product_detail.asp?productid=20 http://commons.wikimedia.org/wiki/Image:Intel_80486DX2_bottom.jpg

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Package Types BGA Ball Grid Array

Verycommonforhighvolumehighpincountchips
200500I/Osiscommon Excellentelectricalcharacteristics GoodheatconductionintoPCboard DifficulttoinspectoncesolderedtoPCboard Difficulttoreplace

BGA with Flip-Chip

EEC116,Winter2010,B.Baas

http://www.mameworld.net/gurudumps/MyStuff/packages.html http://www.pcmag.com/encyclopedia_term/0,2542,t=BGA&i=38577,00.asp 41 http://www.etech-web.com/bga_reballing.htm http://www.tms.org/pubs/journals/JOM/9903/Frear-9903.html

Package Parameters

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Mounting Die Directly to a Substrate

A. MultichipModule
silicononsilicon manyofotherceramicmaterialsused testingisbigissue(knowngooddie)

B. ChipsonBoard C. SysteminPackage(SiP)

EEC116,Winter2010,B.Baas

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Multi-Chip Module

EEC116,Winter2010,B.Baas

Source: Digital Integrated Circuits, 2nd

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Package Types SiP System in Package

Increasinglypopularforhighvolumesmallform factorproducts Cancombinewirebondswith flipchip Nicesolutionforanapplication systemwithdifferenttypesof chipsandpassives (R,L,C)

EEC116,Winter2010,B.Baas

http://www.carsem.com/services/package.php

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