Scribd
Upload
23 views

Virudhunagar 626 005: Sri Vidya College of Engineering and Technology

This document is a test from the M.E VLSI course at Sri Vidya College of Engineering and Technology. It contains 10 multiple choice questions about VLSI design techniques. The questions cover topics like latchup in CMOS circuits, fabrication, inverter ratio, design rules, and CAD tools used in CMOS processes. There are also two long answer questions about CMOS process enhancements, design rule checking, n-well and twin-tub processes, CMOS and NMOS inverters, and technology related CAD issues in CMOS processes.

Uploaded by

princeram123
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
23 views

Virudhunagar 626 005: Sri Vidya College of Engineering and Technology

This document is a test from the M.E VLSI course at Sri Vidya College of Engineering and Technology. It contains 10 multiple choice questions about VLSI design techniques. The questions cover topics like latchup in CMOS circuits, fabrication, inverter ratio, design rules, and CAD tools used in CMOS processes. There are also two long answer questions about CMOS process enhancements, design rule checking, n-well and twin-tub processes, CMOS and NMOS inverters, and technology related CAD issues in CMOS processes.

Uploaded by

princeram123
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 2

Sri Vidya College of Engineering and Technology

Virudhunagar 626 005

Department Duration

: M.E (VLSI) : 1:30

Semester Date

:I : 30/11/2013 Test: INT 1I

Course Co e ! Tit"e : VL #102 ! VLSI Desi$n Te%&ni'ues PART A 1. 2. 3. 1. 2. 5 2 = 10 Mark

(&at is meant )* "at%&+up in CM,S %ir%uits- (Outcome: b, Learning Skills: Understand) De.ine /a)ri%ation- (Outcome: b, Learning Skills: Remember) (&at is meant )* in0erter ratio- (Outcome: b, Learning Skills: Remember) (&at are a"" t&e i..erent "a*out esi$n ru"es- (Outcome: b, Learning Skills: Remember) (&* o 3e $o .or C4D too"s in CM,S- ( Outcome: b, Learning Skills: Understand) PART ! 1"#$2 16 = %0 Mark

5. a) 6rie."* e7p"ain a)out t&e CM,S pro%ess en&an%ements-(Outcome: b, Learning Skills: Understand) &'r( &8) )) Des%ri)e a)out t&e esi$n ru"e %&e%9in$ an %ir%uit e7tra%tion steps use in CM,S(Outcome:bLearning,Skills:Understand) (8) #. a) E7p"ain a)out t&e n+3e"" pro%ess: p+3e"" pro%ess an t3in+tu) pro%ess(Outcome: b, Learning Skills: Understand) (15) &'r( )) Des%ri)e a)out NM,S an CM,S in0erters an t&eir %&ara%teristi%s- (Outcome: b, Learning Skills: Understand) (15) 8. a) (&at is meant )* In0erter ratio- 4n a"so etermine t&e pu"" up to pu"" o3n ratio .or Nmos in0erter ri0en t&rou$& one or more pass transistor-(Outcome: b, Learning Skills: Remember) (15) &'r( )) Des%ri)e a)out t&e te%&no"o$* re"ate C4D issues use in CM,S pro%ess (15) ;repare )* <;.;ries& 4;/ECE= Veri.ie )* <Mr 4.>osep& D&*a"an 4;/ECE= 4ppro0e )* <S.E""amma" ?,D/ECE=

You might also like