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Running The Demo Using HDL Designer: Example: Post P&R Result Targeting A Small Virtex V50-4 (24 Bits Cordic)

To run the demo using HDL Designer, download and unzip the source files, add a library mapping in HDL Designer mapping Modelsim work library to work_mti, select the cordic_tb module and click Modelsim button for simulation, enter tb.do in the do box for initialization, and for synthesis select the Cordic module and click the Spectrum button. An example post-placement and routing result targeted a small Virtex V50-4 FPGA for a 24-bit Cordic design.

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0% found this document useful (0 votes)
20 views

Running The Demo Using HDL Designer: Example: Post P&R Result Targeting A Small Virtex V50-4 (24 Bits Cordic)

To run the demo using HDL Designer, download and unzip the source files, add a library mapping in HDL Designer mapping Modelsim work library to work_mti, select the cordic_tb module and click Modelsim button for simulation, enter tb.do in the do box for initialization, and for synthesis select the Cordic module and click the Spectrum button. An example post-placement and routing result targeted a small Virtex V50-4 FPGA for a 24-bit Cordic design.

Uploaded by

harivarahi
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Running the demo using HDL Designer

Download the source files and unzip to a suitable directory Invoke HDL Designer and add a library mapping for the design, map the Modelsim work library to work_mti. Select the cordic_tb module and click on the Modelsim (or other 3rd party simulator) button for simulation When the simulation dialog box pops up enter tb.do in the do box (Initialization command -do) For synthesis, select the Cordic module and click on the Spectrum/Precision (or other 3rd party synthesiser) button

Example: Post P&R result targeting a small Virtex V50-4 (24 bits Cordic)

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