FPGA Module

Presented By
Natalija Jovanovic ([email protected]) Raj Sood ([email protected]) David Gilon ([email protected])

6.371 Final Project Dec 11th, 2002

PROJECT OVERVIEW
Field Programmable Gate Arrays (FPGA)chips allow hardware developers to simulate circuit designs without having to fabricate and test circuit logic. Typically, many FPGAs would be used together to simulate a circuit or component of a circuit. FPGA chips contain 3 major sets of components: 1. Combination Logic Block (CLB) - contains the basic programmable logic functions and general purpose registers 2. Inter-Cell Switch Matrix (SM) - contains circuitry which allows cells to communicate with one another or with external pins 3. Input/Output pin-management circuitry - allows the chip to communicate with the host system Present in all three components is an embedded set of control/configuration circuitry which once programmed, will determine which logic functions will be implemented in each Combination Logic Block (CLB) as well as how the switch matrix and input/output pins will be configured. The goal of this project was to design a basic CLB and Switch Matrix cell design which could be used to build out a full FPGA network of cells and interconnects. More specifically, we focused on component 1 [CLB] and 2 [Switch Matrix]. Our design creates an FPGA module that is composed of 4 CLB and 4 Switch Matrix Units, which together could be used to simulate simple gate functions, 2,3 or 4 bit counters, and simple adders.

Figure 1. FPGA 4 Cell Module Data Pathways

Switch Matrix 1
9

9 bits

Switch Matrix 3

9 bits

carry bit out

carry bit out

out 8 inputs

Combination Logic Block 1

carry bit in

out

8 inputs

Combination Logic Block 3

carry bit in

Switch Matrix 2

9 bits

Switch Matrix 4

9 bits

carry bit out

carry bit out

out 8 inputs

Combination Logic Block 2

carry bit in

out

8 inputs

Combination Logic Block 4

carry bit in

Figure 1a. FPGA Module Layout

Figure 2. FPGA Module Programming Pathway

Program Enable System Clock Preset Scan Data In

Switch Matrix 1

Switch Matrix 3

Combination Logic Block 1

Combination Logic Block 3

NOTE: Prorgram Enable and System Clock signals can be routed in parallel to all modules in the sub-matrix. Preset is wired to all CLB cells only

Switch Matrix 2

Switch Matrix 4 Combination Logic Block 2 Combination Logic Block 4

Scan Data Out

Figure 3. Combination Logic Block (CLB) With Input/Output Selectors

Scan Out 8 bit Input Lines Carry Out 3 bit Output Lines

CLB Scan Out DI

CLB Carry Out DO

F0 F1 F2 F3 CLK_EN CLB Scan In Program Enable CLK Preset CLB Carry In

CLB Logic Core

Q X

8 bit config 8 bit config

8 bit config 8 bit config

NOTE: 3 + 8 = 9 (two lines are In/Out)

Scan In

Program Enable

CLK

Preset

Carry In

Figure 3a. CLB Capsule Layout

Figure 4. Combination Logic Block (CLB) Core Function

scan_out C_OUT

DI

0 1 0

DO

F0 F1 F2 F3

F Block
4 Bit Programmable Logic Function ( built in 16 bit Configuration Array ) 0 1

D FD Block
1 Bit Configurable Register

4 ctrl bits

X
scan_in

CEn_input

8 bit Configuration Array

prog_en

scan_in

C_IN

CLK

Preset

Figure 4b. CLB Core Logic

Figure 4c. 8 Bit Scan Chain Configuration Array (A shift register)

scan_out NOTE:

b7

o7

Several instances of this configuration and dual scan chain arrays were developed for specialty layout needs

b6

o6

b5

o5

b4

o4

b3

o3

b2

o2

b1

o1

b0
f3 scan_in program_enable CLK

o0

Figure 4d. Scan Chain Sample Layout (Horizontal Version)

Figure 5. F Block (programmable 4 bit combination logic function)

scan_out

Decoder

NOTE:

f3 f2 f1 f0

1,1,1,1 1,1,1,0 1,1,0,1 1,1,0,0 1,0,1,1 1,0,1,0 1,0,0,1 1,0,0,0 0,1,1,1 0,1,1,0 0,1,0,1 0,1,0,0 0,0,1,1 0,0,1,0 0,0,0,1 0,0,0,0

b15

Each decoder row has a corresponding bit value which is set at configuration time (when program_enable is set high). For example, when f0..f3 are all 0, the tri state inverter infront of b0 register will be enabled, allowing the bit value of the b0 register to transmit to output X T he Program CLK logic allows clocking of the registers only when program_enable is high

12 more bit state units

b2

b1

b0

scan_in

program_enable

CLK

Figure 5a. F Block Programmable Combination Logic

Figure 6. FD Block (programmable 1 bit register)

Preset Preset_Value 1 Master Slave 0 1

0 1

0 1

NOR

CEn_pgm CEn_input

NOR

NOR

CLK

TCLKHI

VSS

TCLKLO

Figure 6a. FD Block Programmable Register

TCLKH

TCLKL

Setting

0 1 0 1

0 0 1 1

Flip Flop Latch on Clock High Latch on Clock Low Pass Through Latch Governed by CE_Input

Figure 7a. Switch Matrix Overview

wires Top 0..8

See figure 7c for allowed pin connections

8 bit Configuration Array 8 bit Configuration Array

wires Bottom 0..8 8

8 bit Configuration Array

wires Left 0..8

8 bit Configuration Array

8 bit Configuration Array

8 wires Right 0..8 8

8 bit Configuration Array 8 bit Configuration Array

0

8 bit Configuration Array

Figure 7b. Reach Out and Touch Someone (64 allowed conn)
wires Top 0..8

8
Disabled Transmission Gate

wires Right 0..8

E A
Enabled Transmission Gate

E 0 8 Transmission Gate Layout 0

1 0 0 0 1 0
8 wires Left 0..8

8 bit Configuration Array

wires Bottom 0..8

Figure 7c. Switch Matrix Allowed Connections (o)

T o p 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 0 o 8 7 6 5 4 3 2 1 o 0 TOP 0 1 - - - - - - - - - o o 2 3 4 5 6 7 8 Right 0 1 2 3 4 5 6 7 8 Bottom 8 7 6 5 4 3 2 1 0 Left 8 7 6 5 4 3 2 1 0

R i g h t

o o o o o o o o o o o

B o t t o m

o o

o o

o o

o o

o o

o o

o o o o o

L e f t

o o o o o o o o o o o o o o o o o o

o o

o o o o o o o o

Figure 7d. Switch Matrix Layout

So what Can We Do With It?

Given the data path specifications and CLB functionality, various simple hardware emulators can be configured. The following are simplified examples of how to route a 2 bit counter which drives off the clock, and of a compound logic function of 8 inputs.

Figure 8. FPGA_Module Data Path Pin Outs Top 0..8

carry_out_top 0

Top 9..17

carry_out_top 1

Left 0..8

SM1

SM3

Right 0..8

CLB_IN_Left 0..2

out

CLB1

CLB3

3
CLB_OUT Right 0..2

Left 9..17

SM2

SM4

Right 9..17

CLB_IN_Left 3..5

out

CLB2
Carry_in_bottom 0

CLB4 Bottom 9..17

Carry_in_bottom 1

3
CLB_OUT Right 3..5

Bottom 0..8

Figure 9. Example 1: A 2 Bit Counter State Machine

SM 1

SM 3

Counter Bit 1

F1 F0

CLB 1 Programing
F0..3 xx01 xx10 xx01 xx00 X 0 1 1 0

SM 2

SM 4

Counter Bit 0
Specifications: - 2 full CLB cells (Both F and FD blocks)

CLB 2 Programing
F0

F0..3 xxx1 xxx0

X 0 1

- 4 Switch nodes (could also use 2) - CLB register configured as positive edge triggered dRegister on the clock - NOTE: NOT ALL SIGNALS SHOWN

Figure 10. Example 2: A Compound Logic Function

SM 1

SM 3

F0 F1 F2 F3

CLB 1
AND(F0,F1,F2,F3)

Q1 Q2

CLB 3
OR(Q1, Q2)

SM 2

SM 4

J0 J1 J2 J3

CLB 2
XOR(J0,J1,J2,J3)

Q2

Specifications:
X = OR( AND(f0,f1,f2,f3 ) , XOR(j0,j1,j2,j3)) - 3 CLB cell function blocks - 4 Switch nodes - NOTE: NOT ALL SIGNALS SHOWN

The Team Effort

Our design effort partitioned along the following architectural components: CLB Programmable Register (Raj) CLB Interconnect (Raj) CLB Programmable Function Block (David) CLB Capsule Layout & Testing (Raj/David) Scan Chain Configuration Cells (David) Switch Matrix Architecture, Layout & Testing (Natalija) Transmission Gate Specialized Scan Chain Layouts For Space Maximization 95% manual wiring Fpga_Module Final Layout (David) Programming Documentation (David) Application Demo for 2 bit counter & compound function (Raj (Natalija& David helped) Presentation (David)

The Results
All Major Subcomponents s.a. CLB Capsule, Switch Matric, Scan Chaining and their subcomponents were successfully logic tested and laid out, and timing tested The final FPGA_MODULE was wired and laid out. Verification was not completed. This was not due to a lack of effort on all counts.

Layout Extracted Timing Tests For

Switch Matrix Min Propagation Between Pins:
.6 nano seconds

CLB Capsule Clock Period Boundary:

Around 40 nano seconds (~25Mhz)

Lessons Learned
Programming an FPGA module by hand is a pain in the back yard. How did those corporate guys do it? Last minute changes to signal routing specifications must sometimes be made to make life easier Switch Matrix spec and I/O Wiring to CLB is key for flexibility in programming Using standard cell designs help in layout and testing LOGIC TEST EVERYTHING !!!! SHOULD HAVE DONE SYSTEM WIDE TESTING EARLIER IS THERE ENOUGH TIME TO TEST EVERYTHING ?? SHOULD HAVE ESTABLISHED BETTER MODULE PROGRAMMING CONVENTIONS FOR EASIER DEBUGGING OF SCAN BITS THIS WAS A REALLY INTERESTING AND FUN PROJECT!!! WE ALL LEARNED A LOT!!!

Programming 1: Overview
I. Overview The FPGA Module can be programmed with a serial bit sequence when the pen_in signal is high. the s_in terminal is the interface to the module scan chain which travels through all the subcomponents of the module. The programming documentation is also written in the FPGA.SLS file. Each bit in the chain should be timed with a rising clock edge and must be held for the full duration of the clock period. or 2 period counts in the Simeye simulation. For example, to program a high, low, high bit sequence into a component, do the following: set sys_clk = h*1 l*1 h*1 l*1 h*1 l*1 set pen_in = h*6 set s_in = h*2 l*2 h*2 1 0 1 Some Conventions: XXX = unused bit space OUT1[1..0] = A 2 bit sequence with least significant bit to the right

Programming 2: CLB CORE

II CLB Core Programming: A CLB Core requires 24 bits of programming. of those, on 22 bits are actively used. CLB_CORE_BITs = fb15 fb14 fb13 fb12 fb10 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 fb0 XXX XXX mux3 mux2 pres tll tlh cen fb15..0: Combination logic evaluation bits corresponding to rows 15 through 0 mux2: 0=CO, 1=DI mux3: 0=DO, 1=X cen: 0=input driven, 1= data pass through to flip flop pres: Values loaded in register when Preset signal is high tll(tclock low) tlh(tclock high): Example: 0 = flip flop l = latch on low 0 = latch on high 0 0 1 1 = CEN Input Latch on high 1

set s_in = (h*2 l*2)*8 l*2 l*2 h*2 h*2 l*2 l*2 l*2 h*2 fb15..0 XXX XXX m3 m2 pres tll tlh cen this example can be used with a feedback loop to create a 1 bit counter.

Programming 3: CLB Capsule

III. CLB Capsule Programming In addition to the CLB Core bits, 32 more bits are required for capturing the input mux and output mux settings. These settings allow values to come in from the switch matrix and back out to the switch matrix. The Input wires are generally from the Bottom of the corresponding Switch Matrix (by number), meaning that CLB2 receives inputs from the bottom of Switch Matrix 2 wires B1..B8, corresponding to inputs 0..7. CLB_CAPSULE_BITS = CLB_CORE_BITS + XXX XXX XXX XXX XXX OUT2 OUT2[1..0] OUT1 OUT1[1..0] OUT0 OUT0[1..0] CEn_Sel F1_Sel F2_Sel F3_Sel F4_Sel DI_Sel En Sel En Sel En Sec [2..0] [2..0] [2..0] [2..0] [2..0] [2..0]

Input Mux Values:

For deciding which wires from the routing matrix map onto the CEN, F[0..3] and DI signals which are in the CLB_Core Sel[2..0] => IN[0..7] ---------------------------------------------------------000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

Output Mux Values: For deciding which values go to routing wires on OUT[0..2], which correspond to wires values B[0..2] in the corresponding switch matrices NOTE: Output muxes also must be enabled to drive data Sel[1..0] => Data[0..2] ---------------------------------------------------------00 DO 01 Q 10 X 11 -unused Example: set s_in = (h*2 l*2)*8 l*2 l*2 h*2 h*2 l*2 l*2 l*2 h*2 (l*2)*5 h*2 h*2 l*2 h*2 l*2 h*2 h*2 l*2 l*2 h*4 l*2 h*2 l*4 l*2 h*4 l*2 h*2 l*2 l*4 h*2 l*6 fb15..0 b7 b6 m3 m2 pres tll tlh cen Xtr_St OUT OUT2 OUT OUT1 OUT OUT0 CEn_Sel F0_Sel F1_Sel F2_Sel[2..0] F3_Sel DI_Sel

Programming 4: Switch Matrix

IV . Switch Matrix Programing The switch matrix has 81 connection terminals and 64 allowable connections. Each pin can be connected to 1,2, or 3 pins on a different side. The matrix pins are organized in the following geometry: T0 T1 T2 T3 T4 T5 T6 T7 T8 +-------------------------------+

L0| L1| L2| L3| L4| L5| L6| L7| L8|

Switch Matrix

| +-------------------------------+ B0 B1 B2 B3 B4 B5 B6 B7 B8

|R0 |R1 |R2 |R3 |R4 |R5 |R6 |R7 |R8 |

The matrix is programmed in the following order of below (connection table follows as well) : SM_BITS = HTC[7..0] + VRC[15..8] + HBC[7..0] + VLC[15..8] + HTC[15..8] + VRC[7..0] + HBC[15..8] + VLC[7..0] For example, To make a connection between L0 and B0, bit HTC[7] must be set to high during programming. The table below provides a translation of each config bit to the correlating wire connections. The conventions used will be T0..T8, R0..R8, B0..B8, and L0..L8 corresponding to Top, Right, Bottom, and Left wires.

Programming 4: Cont
Connection bit ----------------L0 - B0 HTC[7] B1 - R0 HTC[6] R1 - T1 HTC[5] R2 - T2 HTC[4] L3 - T2 HTC[3] B2 - R3 HTC[2] R4 - T4 HTC[1] L2 - B2 HTC[0] L3 - B3 L4 - B4 R5 - T5 L5 - B5 R6 - T6 R6 - B7 R7 - T7 L7 - B7 L7 - R8 L6 - R7 L5 - B8 R5 - L5 L2 - R3 L1 - R2 L0 - R1 B7 - T8 B0 - T0 B1 - T1 B2 - T2 B3 - T3 B4 - T4 B5 - T5 B6 - T6 B7 - T7 VRC[15] VRC[14] VRC[13] VRC[12] VRC[11] VRC[10] VRC[9] VRC[8] HBC[7] HBC[6] HBC[5] HBC[4] HBC[3] HBC[2] HBC[1] HBC[0] VLC[15] VLC[14] VLC[13] VLC[12] VLC[11] VLC[10] VLC[9] VLC[8] R0 - T0 B0 - T1 L1 - T0 L2 - T3 B3 - R2 R3 - T3 L4 - T5 L1 - B1 R5 - B4 L6 - B6 L6 - T7 L7 - T6 R7 - B6 B8 - L8 B8 - R8 R8 - T8 L8 - T8 R8 - L8 R7 - L7 R6 - L6 R4 - L4 R3 - L3 R2 - L2 R1 - L1 B1 - T2 B2 - T3 B3 - T4 B4 - T5 B5 - T6 B6 - T7 B8 - T8 R0 - L0 HTC[15] HTC[14] HTC[13] HTC[12] HTC[11] HTC[10] HTC[9] HTC[8] VRC[7] VRC[6] VRC[5] VRC[4] VRC[3] VRC[2] VRC[1] VRC[0] HBC[15] HBC[14] HBC[13] HBC[12] HBC[11] HBC[10] HBC[9] HBC[8] VLC[7] VLC[6] VLC[5] VLC[4] VLC[3] VLC[2] VLC[1] VLC[0]

Programming 5: Putting it All together

Full Module Programing. Now that the the programmer knows how to set the bit sequence for each component in the module, the final bit sequence is the serial sequence of bits of each component in the following order: MODULE_BITS = CLB2 + CLB4 + CLB3 + CLB1 + SM2 + SM4 + SM3 + SM1

Simulations

Example 2: Compound Function Logic Sim

CLB Capsule Timing Simulations

Other Logic Simulations

CLB Capsule Simulation Emulating Programming And Execution Of a 1 Bit Counter (also tested a two Bit counter cmd) Execution

Programming (in the red box)

Programming

CLB CORE Simulation Emulating Programming And Execution Of a 1 Bit Counter With Flip Flop mode

Inputs F0..1 D and Q outputs

CLB CORE Simulation Testing CE_Latch mode

Programmable F Block (4 bit Combination Logic) Scan in values And read out

Programmable FD Block (1 bit register) All Flip Flop Modes Tested

8 Bit Scan Chain Programming Example

Switch Matrix Configuration Scan Box Logic Simulation Programming

Switch Matrix Pin Connection Logic Simulation Programming Single Connection

A single Transmission Gate Configured On

Terminals T8 and B8 connected